Simulation Results: rstmgr

 
27/08/2026 21:36:35 DVSim: v1.52.0 sha: 72ff50e json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 96.66 %
  • code
  • 99.21 %
  • assert
  • 97.99 %
  • func
  • 92.77 %
  • line
  • 99.19 %
  • branch
  • 99.72 %
  • cond
  • 98.30 %
  • toggle
  • 99.62 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
rstmgr_smoke 1.790s 75.780us 1 1 100.00
csr_hw_reset 1 1 100.00
rstmgr_csr_hw_reset 1.520s 92.136us 1 1 100.00
csr_rw 1 1 100.00
rstmgr_csr_rw 1.200s 37.035us 1 1 100.00
csr_bit_bash 1 1 100.00
rstmgr_csr_bit_bash 5.860s 236.154us 1 1 100.00
csr_aliasing 1 1 100.00
rstmgr_csr_aliasing 1.280s 36.628us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
rstmgr_csr_mem_rw_with_rand_reset 2.000s 98.867us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
rstmgr_csr_rw 1.200s 37.035us 1 1 100.00
rstmgr_csr_aliasing 1.280s 36.628us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
reset_stretcher 1 1 100.00
rstmgr_por_stretcher 1.410s 87.642us 1 1 100.00
sw_rst 1 1 100.00
rstmgr_sw_rst 1.540s 42.272us 1 1 100.00
sw_rst_reset_race 1 1 100.00
rstmgr_sw_rst_reset_race 1.300s 45.251us 1 1 100.00
reset_info 1 1 100.00
rstmgr_reset 6.240s 668.159us 1 1 100.00
cpu_info 1 1 100.00
rstmgr_reset 6.240s 668.159us 1 1 100.00
alert_info 1 1 100.00
rstmgr_reset 6.240s 668.159us 1 1 100.00
reset_info_capture 1 1 100.00
rstmgr_reset 6.240s 668.159us 1 1 100.00
stress_all 1 1 100.00
rstmgr_stress_all 2.260s 142.120us 1 1 100.00
alert_test 1 1 100.00
rstmgr_alert_test 1.240s 38.234us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
rstmgr_tl_errors 1.980s 41.946us 1 1 100.00
tl_d_illegal_access 1 1 100.00
rstmgr_tl_errors 1.980s 41.946us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
rstmgr_csr_hw_reset 1.520s 92.136us 1 1 100.00
rstmgr_csr_rw 1.200s 37.035us 1 1 100.00
rstmgr_csr_aliasing 1.280s 36.628us 1 1 100.00
rstmgr_same_csr_outstanding 1.780s 74.712us 1 1 100.00
tl_d_partial_access 4 4 100.00
rstmgr_csr_hw_reset 1.520s 92.136us 1 1 100.00
rstmgr_csr_rw 1.200s 37.035us 1 1 100.00
rstmgr_csr_aliasing 1.280s 36.628us 1 1 100.00
rstmgr_same_csr_outstanding 1.780s 74.712us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
rstmgr_sec_cm 23.690s 3390.568us 1 1 100.00
rstmgr_tl_intg_err 3.490s 349.579us 1 1 100.00
prim_count_check 1 1 100.00
rstmgr_sec_cm 23.690s 3390.568us 1 1 100.00
prim_fsm_check 1 1 100.00
rstmgr_sec_cm 23.690s 3390.568us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
rstmgr_tl_intg_err 3.490s 349.579us 1 1 100.00
sec_cm_scan_intersig_mubi 1 1 100.00
rstmgr_sec_cm_scan_intersig_mubi 1.550s 63.333us 1 1 100.00
sec_cm_leaf_rst_bkgn_chk 1 1 100.00
rstmgr_leaf_rst_cnsty 6.320s 465.016us 1 1 100.00
sec_cm_leaf_rst_shadow 1 1 100.00
rstmgr_leaf_rst_shadow_attack 3.450s 293.281us 1 1 100.00
sec_cm_leaf_fsm_sparse 1 1 100.00
rstmgr_sec_cm 23.690s 3390.568us 1 1 100.00
sec_cm_sw_rst_config_regwen 1 1 100.00
rstmgr_csr_rw 1.200s 37.035us 1 1 100.00
sec_cm_dump_ctrl_config_regwen 1 1 100.00
rstmgr_csr_rw 1.200s 37.035us 1 1 100.00