Simulation Results

Simulation Results: rv_dm/use_dmi_interface

27/08/2026 21:36:35 DVSim: v1.52.0 sha: 72ff50e json Branch: master Tool: xcelium [24.03-s007]

Coverage statistics

Total
87.44 %

code
74.47 %

assert
96.51 %

func
91.35 %

block
90.19 %

line
90.09 %

branch
73.39 %

toggle
71.91 %

FSM
62.50 %

Validation stages

V1		92.59%
V2		69.57%
V2S		100.00%
V3		100.00%
unmapped		0.00%

25/27 passed

92.59 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
smoke				1	1	100.00
	rv_dm_smoke	47.000s	3459.488us	1	1	100.00
jtag_dtm_csr_hw_reset				1	1	100.00
	rv_dm_jtag_dtm_csr_hw_reset	45.000s	1133.262us	1	1	100.00
jtag_dtm_csr_rw				1	1	100.00
	rv_dm_jtag_dtm_csr_rw	46.000s	162.904us	1	1	100.00
jtag_dtm_csr_bit_bash				1	1	100.00
	rv_dm_jtag_dtm_csr_bit_bash	52.000s	8218.353us	1	1	100.00
jtag_dtm_csr_aliasing				1	1	100.00
	rv_dm_jtag_dtm_csr_aliasing	42.000s	450.029us	1	1	100.00
jtag_dmi_csr_hw_reset				1	1	100.00
	rv_dm_jtag_dmi_csr_hw_reset	47.000s	3635.505us	1	1	100.00
jtag_dmi_csr_rw				1	1	100.00
	rv_dm_jtag_dmi_csr_rw	57.000s	3199.374us	1	1	100.00
jtag_dmi_csr_bit_bash				1	1	100.00
	rv_dm_jtag_dmi_csr_bit_bash	53.000s	25943.248us	1	1	100.00
jtag_dmi_csr_aliasing				1	1	100.00
	rv_dm_jtag_dmi_csr_aliasing	43.000s	3765.560us	1	1	100.00
jtag_dmi_cmderr_busy				1	1	100.00
	rv_dm_cmderr_busy	47.000s	243.537us	1	1	100.00
jtag_dmi_cmderr_not_supported				1	1	100.00
	rv_dm_cmderr_not_supported	45.000s	172.463us	1	1	100.00
cmderr_exception				1	1	100.00
	rv_dm_cmderr_exception	52.000s	357.653us	1	1	100.00
mem_tl_access_resuming				0	1	0.00
	rv_dm_mem_tl_access_resuming	37.000s	136.722us	0	1	0.00
mem_tl_access_halted				1	1	100.00
	rv_dm_mem_tl_access_halted	48.000s	115.808us	1	1	100.00
cmderr_halt_resume				1	1	100.00
	rv_dm_cmderr_halt_resume	45.000s	964.882us	1	1	100.00
dataaddr_rw_access				1	1	100.00
	rv_dm_dataaddr_rw_access	45.000s	70.724us	1	1	100.00
halt_resume				1	1	100.00
	rv_dm_halt_resume_whereto	44.000s	232.702us	1	1	100.00
progbuf_busy				1	1	100.00
	rv_dm_cmderr_busy	47.000s	243.537us	1	1	100.00
abstractcmd_status				1	1	100.00
	rv_dm_abstractcmd_status	49.000s	80.204us	1	1	100.00
progbuf_read_write_execute				1	1	100.00
	rv_dm_progbuf_read_write_execute	36.000s	472.026us	1	1	100.00
progbuf_exception				1	1	100.00
	rv_dm_cmderr_exception	52.000s	357.653us	1	1	100.00
rom_read_access				0	1	0.00
	rv_dm_rom_read_access	47.000s	30.445us	0	1	0.00
csr_hw_reset				1	1	100.00
	rv_dm_csr_hw_reset	45.000s	309.566us	1	1	100.00
csr_rw				1	1	100.00
	rv_dm_csr_rw	50.000s	196.677us	1	1	100.00
csr_bit_bash				1	1	100.00
	rv_dm_csr_bit_bash	73.000s	4160.403us	1	1	100.00
csr_aliasing				1	1	100.00
	rv_dm_csr_aliasing	55.000s	1488.704us	1	1	100.00
csr_mem_rw_with_rand_reset				1	1	100.00
	rv_dm_csr_mem_rw_with_rand_reset	42.000s	158.480us	1	1	100.00
regwen_csr_and_corresponding_lockable_csr				2	2	100.00
	rv_dm_csr_aliasing	55.000s	1488.704us	1	1	100.00
	rv_dm_csr_rw	50.000s	196.677us	1	1	100.00
mem_walk				1	1	100.00
	rv_dm_mem_walk	42.000s	176.099us	1	1	100.00
mem_partial_access				1	1	100.00
	rv_dm_mem_partial_access	54.000s	106.531us	1	1	100.00

16/23 passed

69.57 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
idcode				1	1	100.00
	rv_dm_smoke	47.000s	3459.488us	1	1	100.00
jtag_dtm_hard_reset				1	1	100.00
	rv_dm_jtag_dtm_hard_reset	54.000s	665.267us	1	1	100.00
jtag_dtm_idle_hint				1	1	100.00
	rv_dm_jtag_dtm_idle_hint	46.000s	281.819us	1	1	100.00
jtag_dmi_failed_op				1	1	100.00
	rv_dm_dmi_failed_op	39.000s	531.230us	1	1	100.00
jtag_dmi_dm_inactive				1	1	100.00
	rv_dm_jtag_dmi_dm_inactive	40.000s	2200.074us	1	1	100.00
sba				0	2	0.00
	rv_dm_sba_tl_access	42.000s	4052.928us	0	1	0.00
	rv_dm_delayed_resp_sba_tl_access	50.000s	199.506us	0	1	0.00
bad_sba				0	1	0.00
	rv_dm_bad_sba_tl_access	50.000s	797.034us	0	1	0.00
sba_autoincrement				0	1	0.00
	rv_dm_autoincr_sba_tl_access	44.000s	627.484us	0	1	0.00
jtag_dmi_debug_disabled				0	1	0.00
	rv_dm_jtag_dmi_debug_disabled	49.000s	147.241us	0	1	0.00
sba_debug_disabled				1	1	100.00
	rv_dm_sba_debug_disabled	42.000s	990.811us	1	1	100.00
ndmreset_req				1	1	100.00
	rv_dm_ndmreset_req	42.000s	153.826us	1	1	100.00
hart_unavail				0	1	0.00
	rv_dm_hart_unavail	49.000s	136.250us	0	1	0.00
tap_ctrl_transitions				2	2	100.00
	rv_dm_tap_fsm	62.000s	14525.307us	1	1	100.00
	rv_dm_tap_fsm_rand_reset	63.000s	1879.689us	1	1	100.00
hartsel_warl				1	1	100.00
	rv_dm_hartsel_warl	50.000s	140.749us	1	1	100.00
stress_all				0	1	0.00
	rv_dm_stress_all	4854.000s	10000000.000us	0	1	0.00
alert_test				1	1	100.00
	rv_dm_alert_test	38.000s	72.042us	1	1	100.00
tl_d_oob_addr_access				1	1	100.00
	rv_dm_tl_errors	42.000s	817.899us	1	1	100.00
tl_d_illegal_access				1	1	100.00
	rv_dm_tl_errors	42.000s	817.899us	1	1	100.00
tl_d_outstanding_access				4	4	100.00
	rv_dm_csr_aliasing	55.000s	1488.704us	1	1	100.00
	rv_dm_csr_hw_reset	45.000s	309.566us	1	1	100.00
	rv_dm_csr_rw	50.000s	196.677us	1	1	100.00
	rv_dm_same_csr_outstanding	42.000s	166.236us	1	1	100.00
tl_d_partial_access				4	4	100.00
	rv_dm_csr_aliasing	55.000s	1488.704us	1	1	100.00
	rv_dm_csr_hw_reset	45.000s	309.566us	1	1	100.00
	rv_dm_csr_rw	50.000s	196.677us	1	1	100.00
	rv_dm_same_csr_outstanding	42.000s	166.236us	1	1	100.00

V2S

7/7 passed

100.00 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
tl_intg_err				2	2	100.00
	rv_dm_sec_cm	50.000s	810.867us	1	1	100.00
	rv_dm_tl_intg_err	45.000s	2264.005us	1	1	100.00
sec_cm_bus_integrity				1	1	100.00
	rv_dm_tl_intg_err	45.000s	2264.005us	1	1	100.00
sec_cm_lc_hw_debug_en_intersig_mubi				2	2	100.00
	rv_dm_sba_debug_disabled	42.000s	990.811us	1	1	100.00
	rv_dm_debug_disabled	42.000s	54.483us	1	1	100.00
sec_cm_lc_dft_en_intersig_mubi				2	2	100.00
	rv_dm_sba_debug_disabled	42.000s	990.811us	1	1	100.00
	rv_dm_debug_disabled	42.000s	54.483us	1	1	100.00
sec_cm_otp_dis_rv_dm_late_debug_intersig_mubi				1	1	100.00
	rv_dm_smoke	47.000s	3459.488us	1	1	100.00
sec_cm_dm_en_ctrl_lc_gated				1	1	100.00
	rv_dm_buffered_enable	41.000s	645.644us	1	1	100.00
sec_cm_sba_tl_lc_gate_fsm_sparse				1	1	100.00
	rv_dm_sparse_lc_gate_fsm	39.000s	101.799us	1	1	100.00
sec_cm_mem_tl_lc_gate_fsm_sparse				1	1	100.00
	rv_dm_sparse_lc_gate_fsm	39.000s	101.799us	1	1	100.00
sec_cm_exec_ctrl_mubi				1	1	100.00
	rv_dm_buffered_enable	41.000s	645.644us	1	1	100.00

1/1 passed

100.00 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
stress_all_with_rand_reset				1	1	100.00
	rv_dm_stress_all_with_rand_reset	65.000s	1346.811us	1	1	100.00

unmapped

0/1 passed

0.00 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
Unmapped				0	1	0.00
	rv_dm_scanmode	229.000s	300000.000us	0	1	0.00

Error Messages

	Test	seed	line	log context
UVM_ERROR (rv_dm_scoreboard.sv:481) [scoreboard] sba_tl_access_q item uncompared:				2 test runs
	rv_dm_sba_tl_access	4623457773329205768863218641435730907964835965835835592238112717451304013155	87	------------------------------------------------------------------- Name Type Size Value ------------------------------------------------------------------- req cip_tl_seq_item - @23836
	rv_dm_bad_sba_tl_access	11846988569110998615666187341895193279922388087570939717111250355809836008587	96	------------------------------------------------------------------- Name Type Size Value ------------------------------------------------------------------- req cip_tl_seq_item - @23839
UVM_FATAL (tl_device_seq.sv:151) sequencer [m_tl_sba_device_seq] Cannot randomize rsp				2 test runs
	rv_dm_delayed_resp_sba_tl_access	29115509404238752446556363172365405716134675027625799421475428110596058779710	107	UVM_INFO @ 199505579 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rv_dm_autoincr_sba_tl_access	68684784977269040230372438618447864793253691137762553499137382035926337569527	107	UVM_INFO @ 627484087 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_FATAL (uvm_phase.svh:1521) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue				2 test runs
	rv_dm_scanmode	15028586509903992497268720256925688327077140236675119097000116120410515454131	87	UVM_INFO @ 300000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rv_dm_stress_all	62084652570820177009476655300857830474713258145967413776528409369243558281757	92	UVM_INFO @ 10000000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_ERROR (rv_dm_mem_tl_access_resuming_vseq.sv:56) [rv_dm_mem_tl_access_resuming_vseq] Check failed jtag_dmi_ral.dmstatus.anyhalted.get_mirrored_value() == 'b (* [] vs [*])				1 test run
	rv_dm_mem_tl_access_resuming	68921269963714204301299846412671486108754420350878853938590297038292052397958	87	UVM_INFO @ 136722300 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_ERROR (rv_dm_hart_unavail_vseq.sv:24) [rv_dm_hart_unavail_vseq] Check failed jtag_dmi_ral.dmstatus.anyunavail.get_mirrored_value() == req_unavailable (* [] vs [*])				1 test run
	rv_dm_hart_unavail	99546783738149029082086015055770623637272528418619240644514109729906313739623	87	UVM_INFO @ 136249755 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_ERROR (rv_dm_jtag_dmi_debug_disabled_vseq.sv:16) [rv_dm_jtag_dmi_debug_disabled_vseq] Check failed rdata == expected_value (* [] vs [*])				1 test run
	rv_dm_jtag_dmi_debug_disabled	45204702281981130546951469173458557778623841667903482974387297230041772244915	87	UVM_INFO @ 147240813 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_ERROR (rv_dm_scoreboard.sv:409) scoreboard [scoreboard] Unexpected response to read from address * in mem reg block. Problems: '{"Expected read d_data=, but it was "}. Item: (req: (cip_tl_seq_item@23867) { a_addr: * a_data: * a_mask: * a_size: * a_param: * a_source: * a_opcode: * a_user: * d_param: * d_source: * d_data: * d_size: * d_opcode: * d_error: * d_sink: * d_user: * a_valid_delay: * d_valid_delay: * a_valid_len: * d_valid_len: * req_abort_after_a_valid_len: * rsp_abort_after_d_valid_len: * req_completed: * rsp_completed: * tl_intg_err_type: TlIntgErrNone max_ecc_errors: * }				1 test run
	rv_dm_rom_read_access	48005613996643987680240161959008714523421609815513582025344328614724265574302	87	). UVM_INFO @ 30445045 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---