Simulation Results: rv_timer

 
27/08/2026 21:36:35 DVSim: v1.52.0 sha: 72ff50e json Branch: master Tool: xcelium [24.03-s007]
Coverage statistics
  • Total
  • 95.66 %
  • code
  • 90.45 %
  • assert
  • 96.52 %
  • func
  • 100.00 %
  • block
  • 99.10 %
  • line
  • 99.02 %
  • branch
  • 99.26 %
  • toggle
  • 73.08 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
V3
33.33%
Testpoint Test Max Runtime Sim Time Pass Total %
random 1 1 100.00
rv_timer_random 2.000s 465.785us 1 1 100.00
csr_hw_reset 1 1 100.00
rv_timer_csr_hw_reset 1.000s 34.164us 1 1 100.00
csr_rw 1 1 100.00
rv_timer_csr_rw 1.000s 13.518us 1 1 100.00
csr_bit_bash 1 1 100.00
rv_timer_csr_bit_bash 2.000s 199.244us 1 1 100.00
csr_aliasing 1 1 100.00
rv_timer_csr_aliasing 1.000s 13.967us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
rv_timer_csr_mem_rw_with_rand_reset 2.000s 15.236us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
rv_timer_csr_rw 1.000s 13.518us 1 1 100.00
rv_timer_csr_aliasing 1.000s 13.967us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
random_reset 1 1 100.00
rv_timer_random_reset 2.000s 287.761us 1 1 100.00
disabled 1 1 100.00
rv_timer_disabled 3.000s 1152.917us 1 1 100.00
cfg_update_on_fly 1 1 100.00
rv_timer_cfg_update_on_fly 43.000s 47731.275us 1 1 100.00
no_interrupt_test 1 1 100.00
rv_timer_cfg_update_on_fly 43.000s 47731.275us 1 1 100.00
stress 1 1 100.00
rv_timer_stress_all 12.000s 5932.107us 1 1 100.00
alert_test 1 1 100.00
rv_timer_alert_test 1.000s 35.634us 1 1 100.00
intr_test 1 1 100.00
rv_timer_intr_test 1.000s 62.457us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
rv_timer_tl_errors 2.000s 182.004us 1 1 100.00
tl_d_illegal_access 1 1 100.00
rv_timer_tl_errors 2.000s 182.004us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
rv_timer_csr_hw_reset 1.000s 34.164us 1 1 100.00
rv_timer_csr_rw 1.000s 13.518us 1 1 100.00
rv_timer_csr_aliasing 1.000s 13.967us 1 1 100.00
rv_timer_same_csr_outstanding 2.000s 31.681us 1 1 100.00
tl_d_partial_access 4 4 100.00
rv_timer_csr_hw_reset 1.000s 34.164us 1 1 100.00
rv_timer_csr_rw 1.000s 13.518us 1 1 100.00
rv_timer_csr_aliasing 1.000s 13.967us 1 1 100.00
rv_timer_same_csr_outstanding 2.000s 31.681us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
rv_timer_sec_cm 1.000s 283.861us 1 1 100.00
rv_timer_tl_intg_err 2.000s 1068.857us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
rv_timer_tl_intg_err 2.000s 1068.857us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
min_value 0 1 0.00
rv_timer_min 1.000s 53.376us 0 1 0.00
max_value 0 1 0.00
rv_timer_max 1.000s 47.111us 0 1 0.00
stress_all_with_rand_reset 1 1 100.00
rv_timer_stress_all_with_rand_reset 49.000s 58743.170us 1 1 100.00

Error Messages

   Test seed line log context
UVM_FATAL (rv_timer_base_vseq.sv:183) [intr_state_spinwait] timeout rv_timer_reg_block.intr_state* (addr=*) == * 1 test run
rv_timer_min 76403923204787045013307019883005573899453791613392888351719551692826637068890 84
UVM_INFO @ 53375825 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (rv_timer_scoreboard.sv:227) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*]) 1 test run
rv_timer_max 61980592795713505660775400798279808331837697045892863815655091754060467337000 84
UVM_INFO @ 47111132 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---