Simulation Results: spi_device/1r1w

 
27/08/2026 21:36:35 DVSim: v1.52.0 sha: 72ff50e json Branch: master Tool: xcelium [24.03-s007]
Coverage statistics
  • Total
  • 85.26 %
  • code
  • 89.48 %
  • assert
  • 95.02 %
  • func
  • 71.27 %
  • block
  • 98.34 %
  • line
  • 98.75 %
  • branch
  • 96.99 %
  • toggle
  • 72.61 %
  • FSM
  • 89.58 %
Validation stages
V1
100.00%
V2
92.59%
V2S
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
spi_device_flash_and_tpm 456.000s 83282.267us 1 1 100.00
csr_hw_reset 1 1 100.00
spi_device_csr_hw_reset 2.000s 37.186us 1 1 100.00
csr_rw 1 1 100.00
spi_device_csr_rw 3.000s 197.720us 1 1 100.00
csr_bit_bash 1 1 100.00
spi_device_csr_bit_bash 25.000s 1176.252us 1 1 100.00
csr_aliasing 1 1 100.00
spi_device_csr_aliasing 2.000s 77.125us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
spi_device_csr_mem_rw_with_rand_reset 3.000s 185.589us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
spi_device_csr_rw 3.000s 197.720us 1 1 100.00
spi_device_csr_aliasing 2.000s 77.125us 1 1 100.00
mem_walk 1 1 100.00
spi_device_mem_walk 1.000s 37.276us 1 1 100.00
mem_partial_access 1 1 100.00
spi_device_mem_partial_access 2.000s 93.000us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
csb_read 1 1 100.00
spi_device_csb_read 2.000s 77.561us 1 1 100.00
mem_parity 0 1 0.00
spi_device_mem_parity 2.000s 4.830us 0 1 0.00
mem_cfg 0 1 0.00
spi_device_ram_cfg 1.000s 17.364us 0 1 0.00
tpm_read 1 1 100.00
spi_device_tpm_rw 1.000s 11.454us 1 1 100.00
tpm_write 1 1 100.00
spi_device_tpm_rw 1.000s 11.454us 1 1 100.00
tpm_hw_reg 2 2 100.00
spi_device_tpm_read_hw_reg 36.000s 7049.134us 1 1 100.00
spi_device_tpm_sts_read 2.000s 66.214us 1 1 100.00
tpm_fully_random_case 1 1 100.00
spi_device_tpm_all 8.000s 338.620us 1 1 100.00
pass_cmd_filtering 2 2 100.00
spi_device_pass_cmd_filtering 8.000s 808.549us 1 1 100.00
spi_device_flash_all 255.000s 16578.168us 1 1 100.00
pass_addr_translation 2 2 100.00
spi_device_pass_addr_payload_swap 22.000s 9722.102us 1 1 100.00
spi_device_flash_all 255.000s 16578.168us 1 1 100.00
pass_payload_translation 2 2 100.00
spi_device_pass_addr_payload_swap 22.000s 9722.102us 1 1 100.00
spi_device_flash_all 255.000s 16578.168us 1 1 100.00
cmd_info_slots 1 1 100.00
spi_device_flash_all 255.000s 16578.168us 1 1 100.00
cmd_read_status 2 2 100.00
spi_device_intercept 39.000s 1884.442us 1 1 100.00
spi_device_flash_all 255.000s 16578.168us 1 1 100.00
cmd_read_jedec 2 2 100.00
spi_device_intercept 39.000s 1884.442us 1 1 100.00
spi_device_flash_all 255.000s 16578.168us 1 1 100.00
cmd_read_sfdp 2 2 100.00
spi_device_intercept 39.000s 1884.442us 1 1 100.00
spi_device_flash_all 255.000s 16578.168us 1 1 100.00
cmd_fast_read 2 2 100.00
spi_device_intercept 39.000s 1884.442us 1 1 100.00
spi_device_flash_all 255.000s 16578.168us 1 1 100.00
cmd_read_pipeline 2 2 100.00
spi_device_intercept 39.000s 1884.442us 1 1 100.00
spi_device_flash_all 255.000s 16578.168us 1 1 100.00
flash_cmd_upload 1 1 100.00
spi_device_upload 8.000s 1464.911us 1 1 100.00
mailbox_command 1 1 100.00
spi_device_mailbox 38.000s 1381.002us 1 1 100.00
mailbox_cross_outside_command 1 1 100.00
spi_device_mailbox 38.000s 1381.002us 1 1 100.00
mailbox_cross_inside_command 1 1 100.00
spi_device_mailbox 38.000s 1381.002us 1 1 100.00
cmd_read_buffer 2 2 100.00
spi_device_flash_mode 11.000s 814.567us 1 1 100.00
spi_device_read_buffer_direct 15.000s 2029.565us 1 1 100.00
cmd_dummy_cycle 2 2 100.00
spi_device_mailbox 38.000s 1381.002us 1 1 100.00
spi_device_flash_all 255.000s 16578.168us 1 1 100.00
quad_spi 1 1 100.00
spi_device_flash_all 255.000s 16578.168us 1 1 100.00
dual_spi 1 1 100.00
spi_device_flash_all 255.000s 16578.168us 1 1 100.00
4b_3b_feature 1 1 100.00
spi_device_cfg_cmd 9.000s 813.244us 1 1 100.00
write_enable_disable 1 1 100.00
spi_device_cfg_cmd 9.000s 813.244us 1 1 100.00
flash_mode_ignore_cmds 1 1 100.00
spi_device_flash_mode_ignore_cmds 75.000s 3816.062us 1 1 100.00
TPM_with_flash_or_passthrough_mode 1 1 100.00
spi_device_flash_and_tpm 456.000s 83282.267us 1 1 100.00
tpm_and_flash_trans_with_min_inactive_time 1 1 100.00
spi_device_flash_and_tpm_min_idle 366.000s 38684.947us 1 1 100.00
stress_all 1 1 100.00
spi_device_stress_all 185.000s 6336.237us 1 1 100.00
alert_test 1 1 100.00
spi_device_alert_test 2.000s 41.890us 1 1 100.00
intr_test 1 1 100.00
spi_device_intr_test 1.000s 118.003us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
spi_device_tl_errors 7.000s 348.329us 1 1 100.00
tl_d_illegal_access 1 1 100.00
spi_device_tl_errors 7.000s 348.329us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
spi_device_csr_hw_reset 2.000s 37.186us 1 1 100.00
spi_device_csr_rw 3.000s 197.720us 1 1 100.00
spi_device_csr_aliasing 2.000s 77.125us 1 1 100.00
spi_device_same_csr_outstanding 4.000s 141.517us 1 1 100.00
tl_d_partial_access 4 4 100.00
spi_device_csr_hw_reset 2.000s 37.186us 1 1 100.00
spi_device_csr_rw 3.000s 197.720us 1 1 100.00
spi_device_csr_aliasing 2.000s 77.125us 1 1 100.00
spi_device_same_csr_outstanding 4.000s 141.517us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
spi_device_sec_cm 2.000s 187.096us 1 1 100.00
spi_device_tl_intg_err 30.000s 880.625us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
spi_device_tl_intg_err 30.000s 880.625us 1 1 100.00

Error Messages

   Test seed line log context
UVM_ERROR (uvm_hdl_inca.c:743) [UVM/DPI/NOBJ1] name tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.mem[*] cannot be resolved to a hdl object (vlog,vhdl,vlog-slice) 1 test run
spi_device_mem_parity 70893088438546501760615229870142183349547770874153088991906103312026231958135 87
UVM_ERROR @ 3750150 ps: (spi_device_mem_parity_vseq.sv:44) [uvm_test_top.env.virtual_sequencer.spi_device_mem_parity_vseq] Check failed (uvm_hdl_read(egress_path, mem_data))
ERROR: VHPI NOTFOUND
Name tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.mem[921] not found within the scope .
UVM_ERROR @ 3750150 ps: (uvm_hdl_inca.c:743) [UVM/DPI/NOBJ2] name tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.mem[921] cannot be resolved to a hdl object (vlog,vhdl,vlog-slice)
UVM_ERROR (spi_device_ram_cfg_vseq.sv:28) [spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (* [*] vs * [*]) 1 test run
spi_device_ram_cfg 105991648021368289713536958897051139965106294409774928263774535567076677648180 85
UVM_ERROR @ 14862957 ps: (spi_device_ram_cfg_vseq.sv:28) [uvm_test_top.env.virtual_sequencer.spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (0x55 [1010101] vs 0x0 [0])
UVM_ERROR @ 14912957 ps: (spi_device_ram_cfg_vseq.sv:28) [uvm_test_top.env.virtual_sequencer.spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (0xda [11011010] vs 0x0 [0])
UVM_ERROR @ 15009957 ps: (spi_device_ram_cfg_vseq.sv:28) [uvm_test_top.env.virtual_sequencer.spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (0x1b3 [110110011] vs 0x0 [0])
UVM_ERROR @ 15034957 ps: (spi_device_ram_cfg_vseq.sv:28) [uvm_test_top.env.virtual_sequencer.spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (0x3cf [1111001111] vs 0x0 [0])