Simulation Results: spi_host

 
27/08/2026 21:36:35 DVSim: v1.52.0 sha: 72ff50e json Branch: master Tool: xcelium [24.03-s007]
Coverage statistics
  • Total
  • 91.63 %
  • code
  • 91.30 %
  • assert
  • 96.22 %
  • func
  • 87.39 %
  • block
  • 96.96 %
  • line
  • 98.76 %
  • branch
  • 93.35 %
  • toggle
  • 73.07 %
  • FSM
  • 100.00 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
spi_host_smoke 28.000s 993.476us 1 1 100.00
csr_hw_reset 1 1 100.00
spi_host_csr_hw_reset 1.000s 33.876us 1 1 100.00
csr_rw 1 1 100.00
spi_host_csr_rw 2.000s 30.141us 1 1 100.00
csr_bit_bash 1 1 100.00
spi_host_csr_bit_bash 2.000s 47.035us 1 1 100.00
csr_aliasing 1 1 100.00
spi_host_csr_aliasing 1.000s 31.635us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
spi_host_csr_mem_rw_with_rand_reset 2.000s 117.233us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
spi_host_csr_rw 2.000s 30.141us 1 1 100.00
spi_host_csr_aliasing 1.000s 31.635us 1 1 100.00
mem_walk 1 1 100.00
spi_host_mem_walk 1.000s 44.262us 1 1 100.00
mem_partial_access 1 1 100.00
spi_host_mem_partial_access 1.000s 52.431us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
performance 1 1 100.00
spi_host_performance 1.000s 22.818us 1 1 100.00
error_event_intr 3 3 100.00
spi_host_overflow_underflow 2.000s 60.855us 1 1 100.00
spi_host_error_cmd 2.000s 61.946us 1 1 100.00
spi_host_event 13.000s 1012.355us 1 1 100.00
clock_rate 1 1 100.00
spi_host_speed 2.000s 26.256us 1 1 100.00
speed 1 1 100.00
spi_host_speed 2.000s 26.256us 1 1 100.00
chip_select_timing 1 1 100.00
spi_host_speed 2.000s 26.256us 1 1 100.00
upper_range_clkdiv 1 1 100.00
spi_host_upper_range_clkdiv 833.000s 44200.369us 1 1 100.00
sw_reset 1 1 100.00
spi_host_sw_reset 7.000s 338.127us 1 1 100.00
passthrough_mode 1 1 100.00
spi_host_passthrough_mode 1.000s 29.965us 1 1 100.00
cpol_cpha 1 1 100.00
spi_host_speed 2.000s 26.256us 1 1 100.00
full_cycle 1 1 100.00
spi_host_speed 2.000s 26.256us 1 1 100.00
duplex 1 1 100.00
spi_host_smoke 28.000s 993.476us 1 1 100.00
tx_rx_only 1 1 100.00
spi_host_smoke 28.000s 993.476us 1 1 100.00
stress_all 1 1 100.00
spi_host_stress_all 20.000s 838.562us 1 1 100.00
spien 1 1 100.00
spi_host_spien 87.000s 17146.601us 1 1 100.00
stall 1 1 100.00
spi_host_status_stall 618.000s 92042.056us 1 1 100.00
Idlecsbactive 1 1 100.00
spi_host_idlecsbactive 3.000s 96.095us 1 1 100.00
data_fifo_status 1 1 100.00
spi_host_overflow_underflow 2.000s 60.855us 1 1 100.00
alert_test 1 1 100.00
spi_host_alert_test 2.000s 19.407us 1 1 100.00
intr_test 1 1 100.00
spi_host_intr_test 1.000s 74.336us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
spi_host_tl_errors 3.000s 66.427us 1 1 100.00
tl_d_illegal_access 1 1 100.00
spi_host_tl_errors 3.000s 66.427us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
spi_host_csr_hw_reset 1.000s 33.876us 1 1 100.00
spi_host_csr_rw 2.000s 30.141us 1 1 100.00
spi_host_csr_aliasing 1.000s 31.635us 1 1 100.00
spi_host_same_csr_outstanding 2.000s 57.687us 1 1 100.00
tl_d_partial_access 4 4 100.00
spi_host_csr_hw_reset 1.000s 33.876us 1 1 100.00
spi_host_csr_rw 2.000s 30.141us 1 1 100.00
spi_host_csr_aliasing 1.000s 31.635us 1 1 100.00
spi_host_same_csr_outstanding 2.000s 57.687us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
spi_host_tl_intg_err 2.000s 148.851us 1 1 100.00
spi_host_sec_cm 1.000s 48.598us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
spi_host_tl_intg_err 2.000s 148.851us 1 1 100.00