Simulation Results: sram_ctrl/main

 
27/08/2026 21:36:35 DVSim: v1.52.0 sha: 72ff50e json Branch: master Tool: xcelium [24.03-s007]
Coverage statistics
  • Total
  • 95.76 %
  • code
  • 94.98 %
  • assert
  • 98.10 %
  • func
  • 94.20 %
  • block
  • 94.48 %
  • line
  • 95.64 %
  • branch
  • 92.86 %
  • toggle
  • 91.41 %
  • FSM
  • 100.00 %
Validation stages
V1
100.00%
V2
100.00%
V2S
80.00%
V3
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
sram_ctrl_smoke 7.000s 1566.534us 1 1 100.00
csr_hw_reset 1 1 100.00
sram_ctrl_csr_hw_reset 1.000s 23.161us 1 1 100.00
csr_rw 1 1 100.00
sram_ctrl_csr_rw 2.000s 44.780us 1 1 100.00
csr_bit_bash 1 1 100.00
sram_ctrl_csr_bit_bash 4.000s 185.433us 1 1 100.00
csr_aliasing 1 1 100.00
sram_ctrl_csr_aliasing 1.000s 108.999us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
sram_ctrl_csr_mem_rw_with_rand_reset 5.000s 743.595us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
sram_ctrl_csr_rw 2.000s 44.780us 1 1 100.00
sram_ctrl_csr_aliasing 1.000s 108.999us 1 1 100.00
mem_walk 1 1 100.00
sram_ctrl_mem_walk 167.000s 13026.299us 1 1 100.00
mem_partial_access 1 1 100.00
sram_ctrl_mem_partial_access 52.000s 5480.026us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
multiple_keys 1 1 100.00
sram_ctrl_multiple_keys 15.000s 1816.477us 1 1 100.00
stress_pipeline 1 1 100.00
sram_ctrl_stress_pipeline 257.000s 5367.638us 1 1 100.00
bijection 1 1 100.00
sram_ctrl_bijection 207.000s 35045.798us 1 1 100.00
access_during_key_req 1 1 100.00
sram_ctrl_access_during_key_req 37.000s 16569.407us 1 1 100.00
lc_escalation 1 1 100.00
sram_ctrl_lc_escalation 26.000s 23586.836us 1 1 100.00
executable 1 1 100.00
sram_ctrl_executable 44.000s 14638.935us 1 1 100.00
partial_access 2 2 100.00
sram_ctrl_partial_access 4.000s 1377.931us 1 1 100.00
sram_ctrl_partial_access_b2b 280.000s 16764.411us 1 1 100.00
max_throughput 3 3 100.00
sram_ctrl_max_throughput 4.000s 670.544us 1 1 100.00
sram_ctrl_throughput_w_partial_write 5.000s 710.947us 1 1 100.00
sram_ctrl_throughput_w_readback 5.000s 683.941us 1 1 100.00
regwen 1 1 100.00
sram_ctrl_regwen 12.000s 8873.955us 1 1 100.00
ram_cfg 1 1 100.00
sram_ctrl_ram_cfg 3.000s 693.347us 1 1 100.00
non_pow2_mem_size 3 3 100.00
sram_ctrl_smoke 7.000s 1566.534us 1 1 100.00
sram_ctrl_partial_access 4.000s 1377.931us 1 1 100.00
sram_ctrl_access_during_key_req 37.000s 16569.407us 1 1 100.00
stress_all 1 1 100.00
sram_ctrl_stress_all 93.000s 50704.694us 1 1 100.00
alert_test 1 1 100.00
sram_ctrl_alert_test 1.000s 22.056us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
sram_ctrl_tl_errors 3.000s 185.033us 1 1 100.00
tl_d_illegal_access 1 1 100.00
sram_ctrl_tl_errors 3.000s 185.033us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
sram_ctrl_csr_hw_reset 1.000s 23.161us 1 1 100.00
sram_ctrl_csr_rw 2.000s 44.780us 1 1 100.00
sram_ctrl_csr_aliasing 1.000s 108.999us 1 1 100.00
sram_ctrl_same_csr_outstanding 2.000s 16.424us 1 1 100.00
tl_d_partial_access 4 4 100.00
sram_ctrl_csr_hw_reset 1.000s 23.161us 1 1 100.00
sram_ctrl_csr_rw 2.000s 44.780us 1 1 100.00
sram_ctrl_csr_aliasing 1.000s 108.999us 1 1 100.00
sram_ctrl_same_csr_outstanding 2.000s 16.424us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
passthru_mem_tl_intg_err 1 1 100.00
sram_ctrl_passthru_mem_tl_intg_err 45.000s 28252.224us 1 1 100.00
tl_intg_err 2 2 100.00
sram_ctrl_sec_cm 8.000s 862.441us 1 1 100.00
sram_ctrl_tl_intg_err 2.000s 300.090us 1 1 100.00
prim_count_check 1 1 100.00
sram_ctrl_sec_cm 8.000s 862.441us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
sram_ctrl_tl_intg_err 2.000s 300.090us 1 1 100.00
sec_cm_ctrl_config_regwen 1 1 100.00
sram_ctrl_regwen 12.000s 8873.955us 1 1 100.00
sec_cm_readback_config_regwen 1 1 100.00
sram_ctrl_regwen 12.000s 8873.955us 1 1 100.00
sec_cm_exec_config_regwen 1 1 100.00
sram_ctrl_csr_rw 2.000s 44.780us 1 1 100.00
sec_cm_exec_config_mubi 1 1 100.00
sram_ctrl_executable 44.000s 14638.935us 1 1 100.00
sec_cm_exec_intersig_mubi 1 1 100.00
sram_ctrl_executable 44.000s 14638.935us 1 1 100.00
sec_cm_lc_hw_debug_en_intersig_mubi 1 1 100.00
sram_ctrl_executable 44.000s 14638.935us 1 1 100.00
sec_cm_lc_escalate_en_intersig_mubi 1 1 100.00
sram_ctrl_lc_escalation 26.000s 23586.836us 1 1 100.00
sec_cm_prim_ram_ctrl_mubi 0 1 0.00
sram_ctrl_mubi_enc_err 3600.000s 0.000us 0 1 0.00
sec_cm_mem_integrity 1 1 100.00
sram_ctrl_passthru_mem_tl_intg_err 45.000s 28252.224us 1 1 100.00
sec_cm_mem_readback 0 1 0.00
sram_ctrl_readback_err 3600.000s 0.000us 0 1 0.00
sec_cm_mem_scramble 1 1 100.00
sram_ctrl_smoke 7.000s 1566.534us 1 1 100.00
sec_cm_addr_scramble 1 1 100.00
sram_ctrl_smoke 7.000s 1566.534us 1 1 100.00
sec_cm_instr_bus_lc_gated 1 1 100.00
sram_ctrl_executable 44.000s 14638.935us 1 1 100.00
sec_cm_ram_tl_lc_gate_fsm_sparse 1 1 100.00
sram_ctrl_sec_cm 8.000s 862.441us 1 1 100.00
sec_cm_key_global_esc 1 1 100.00
sram_ctrl_lc_escalation 26.000s 23586.836us 1 1 100.00
sec_cm_key_local_esc 1 1 100.00
sram_ctrl_sec_cm 8.000s 862.441us 1 1 100.00
sec_cm_init_ctr_redun 1 1 100.00
sram_ctrl_sec_cm 8.000s 862.441us 1 1 100.00
sec_cm_scramble_key_sideload 1 1 100.00
sram_ctrl_smoke 7.000s 1566.534us 1 1 100.00
sec_cm_tlul_fifo_ctr_redun 1 1 100.00
sram_ctrl_sec_cm 8.000s 862.441us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 1 1 100.00
sram_ctrl_stress_all_with_rand_reset 30.000s 4971.195us 1 1 100.00

Error Messages

   Test seed line log context
Job timed out after * minutes 2 test runs
sram_ctrl_readback_err 79768387217687632945324586446199373874507289735866718434210484846783543796554 None
sram_ctrl_mubi_enc_err 29533469634083711657525277876764902443513190705234164698354122000856206981505 None