Simulation Results: sram_ctrl/ret

 
27/08/2026 21:36:35 DVSim: v1.52.0 sha: 72ff50e json Branch: master Tool: xcelium [24.03-s007]
Coverage statistics
  • Total
  • 90.80 %
  • code
  • 80.99 %
  • assert
  • 97.81 %
  • func
  • 93.60 %
  • block
  • 91.17 %
  • line
  • 92.66 %
  • branch
  • 86.34 %
  • toggle
  • 78.28 %
  • FSM
  • 66.67 %
Validation stages
V1
100.00%
V2
100.00%
V2S
80.00%
V3
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
sram_ctrl_smoke 1.000s 37.640us 1 1 100.00
csr_hw_reset 1 1 100.00
sram_ctrl_csr_hw_reset 1.000s 30.415us 1 1 100.00
csr_rw 1 1 100.00
sram_ctrl_csr_rw 1.000s 22.320us 1 1 100.00
csr_bit_bash 1 1 100.00
sram_ctrl_csr_bit_bash 2.000s 135.259us 1 1 100.00
csr_aliasing 1 1 100.00
sram_ctrl_csr_aliasing 1.000s 23.326us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
sram_ctrl_csr_mem_rw_with_rand_reset 2.000s 31.475us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
sram_ctrl_csr_rw 1.000s 22.320us 1 1 100.00
sram_ctrl_csr_aliasing 1.000s 23.326us 1 1 100.00
mem_walk 1 1 100.00
sram_ctrl_mem_walk 7.000s 1527.631us 1 1 100.00
mem_partial_access 1 1 100.00
sram_ctrl_mem_partial_access 3.000s 96.787us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
multiple_keys 1 1 100.00
sram_ctrl_multiple_keys 6.000s 405.058us 1 1 100.00
stress_pipeline 1 1 100.00
sram_ctrl_stress_pipeline 244.000s 13755.909us 1 1 100.00
bijection 1 1 100.00
sram_ctrl_bijection 8.000s 2290.127us 1 1 100.00
access_during_key_req 1 1 100.00
sram_ctrl_access_during_key_req 27.000s 1784.658us 1 1 100.00
lc_escalation 1 1 100.00
sram_ctrl_lc_escalation 2.000s 115.523us 1 1 100.00
executable 1 1 100.00
sram_ctrl_executable 8.000s 1770.026us 1 1 100.00
partial_access 2 2 100.00
sram_ctrl_partial_access 2.000s 51.941us 1 1 100.00
sram_ctrl_partial_access_b2b 271.000s 5590.765us 1 1 100.00
max_throughput 3 3 100.00
sram_ctrl_max_throughput 2.000s 119.721us 1 1 100.00
sram_ctrl_throughput_w_partial_write 2.000s 135.624us 1 1 100.00
sram_ctrl_throughput_w_readback 2.000s 77.453us 1 1 100.00
regwen 1 1 100.00
sram_ctrl_regwen 15.000s 1733.095us 1 1 100.00
ram_cfg 1 1 100.00
sram_ctrl_ram_cfg 1.000s 89.693us 1 1 100.00
non_pow2_mem_size 3 3 100.00
sram_ctrl_smoke 1.000s 37.640us 1 1 100.00
sram_ctrl_partial_access 2.000s 51.941us 1 1 100.00
sram_ctrl_access_during_key_req 27.000s 1784.658us 1 1 100.00
stress_all 1 1 100.00
sram_ctrl_stress_all 34.000s 4451.870us 1 1 100.00
alert_test 1 1 100.00
sram_ctrl_alert_test 2.000s 12.425us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
sram_ctrl_tl_errors 5.000s 146.020us 1 1 100.00
tl_d_illegal_access 1 1 100.00
sram_ctrl_tl_errors 5.000s 146.020us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
sram_ctrl_csr_hw_reset 1.000s 30.415us 1 1 100.00
sram_ctrl_csr_rw 1.000s 22.320us 1 1 100.00
sram_ctrl_csr_aliasing 1.000s 23.326us 1 1 100.00
sram_ctrl_same_csr_outstanding 1.000s 70.777us 1 1 100.00
tl_d_partial_access 4 4 100.00
sram_ctrl_csr_hw_reset 1.000s 30.415us 1 1 100.00
sram_ctrl_csr_rw 1.000s 22.320us 1 1 100.00
sram_ctrl_csr_aliasing 1.000s 23.326us 1 1 100.00
sram_ctrl_same_csr_outstanding 1.000s 70.777us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
passthru_mem_tl_intg_err 1 1 100.00
sram_ctrl_passthru_mem_tl_intg_err 2.000s 220.522us 1 1 100.00
tl_intg_err 2 2 100.00
sram_ctrl_sec_cm 3.000s 167.743us 1 1 100.00
sram_ctrl_tl_intg_err 3.000s 233.838us 1 1 100.00
prim_count_check 1 1 100.00
sram_ctrl_sec_cm 3.000s 167.743us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
sram_ctrl_tl_intg_err 3.000s 233.838us 1 1 100.00
sec_cm_ctrl_config_regwen 1 1 100.00
sram_ctrl_regwen 15.000s 1733.095us 1 1 100.00
sec_cm_readback_config_regwen 1 1 100.00
sram_ctrl_regwen 15.000s 1733.095us 1 1 100.00
sec_cm_exec_config_regwen 1 1 100.00
sram_ctrl_csr_rw 1.000s 22.320us 1 1 100.00
sec_cm_exec_config_mubi 1 1 100.00
sram_ctrl_executable 8.000s 1770.026us 1 1 100.00
sec_cm_exec_intersig_mubi 1 1 100.00
sram_ctrl_executable 8.000s 1770.026us 1 1 100.00
sec_cm_lc_hw_debug_en_intersig_mubi 1 1 100.00
sram_ctrl_executable 8.000s 1770.026us 1 1 100.00
sec_cm_lc_escalate_en_intersig_mubi 1 1 100.00
sram_ctrl_lc_escalation 2.000s 115.523us 1 1 100.00
sec_cm_prim_ram_ctrl_mubi 0 1 0.00
sram_ctrl_mubi_enc_err 3600.000s 0.000us 0 1 0.00
sec_cm_mem_integrity 1 1 100.00
sram_ctrl_passthru_mem_tl_intg_err 2.000s 220.522us 1 1 100.00
sec_cm_mem_readback 0 1 0.00
sram_ctrl_readback_err 3600.000s 0.000us 0 1 0.00
sec_cm_mem_scramble 1 1 100.00
sram_ctrl_smoke 1.000s 37.640us 1 1 100.00
sec_cm_addr_scramble 1 1 100.00
sram_ctrl_smoke 1.000s 37.640us 1 1 100.00
sec_cm_instr_bus_lc_gated 1 1 100.00
sram_ctrl_executable 8.000s 1770.026us 1 1 100.00
sec_cm_ram_tl_lc_gate_fsm_sparse 1 1 100.00
sram_ctrl_sec_cm 3.000s 167.743us 1 1 100.00
sec_cm_key_global_esc 1 1 100.00
sram_ctrl_lc_escalation 2.000s 115.523us 1 1 100.00
sec_cm_key_local_esc 1 1 100.00
sram_ctrl_sec_cm 3.000s 167.743us 1 1 100.00
sec_cm_init_ctr_redun 1 1 100.00
sram_ctrl_sec_cm 3.000s 167.743us 1 1 100.00
sec_cm_scramble_key_sideload 1 1 100.00
sram_ctrl_smoke 1.000s 37.640us 1 1 100.00
sec_cm_tlul_fifo_ctr_redun 1 1 100.00
sram_ctrl_sec_cm 3.000s 167.743us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 1 1 100.00
sram_ctrl_stress_all_with_rand_reset 45.000s 2008.993us 1 1 100.00

Error Messages

   Test seed line log context
Job timed out after * minutes 2 test runs
sram_ctrl_readback_err 5461415121210676930323578378632427534017084003178998249403011389500141608356 None
sram_ctrl_mubi_enc_err 111425027461644021621887035750395958817841027172748925330056500573990960004628 None