Simulation Results: uart

 
27/08/2026 21:36:35 DVSim: v1.52.0 sha: 72ff50e json Branch: master Tool: xcelium [24.03-s007]
Coverage statistics
  • Total
  • 93.45 %
  • code
  • 92.53 %
  • assert
  • 97.12 %
  • func
  • 90.69 %
  • block
  • 98.83 %
  • line
  • 99.24 %
  • branch
  • 97.79 %
  • toggle
  • 73.08 %
  • FSM
  • 100.00 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
V3
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
uart_smoke 10.000s 5556.902us 1 1 100.00
csr_hw_reset 1 1 100.00
uart_csr_hw_reset 1.000s 26.627us 1 1 100.00
csr_rw 1 1 100.00
uart_csr_rw 1.000s 62.190us 1 1 100.00
csr_bit_bash 1 1 100.00
uart_csr_bit_bash 3.000s 1339.270us 1 1 100.00
csr_aliasing 1 1 100.00
uart_csr_aliasing 1.000s 14.119us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
uart_csr_mem_rw_with_rand_reset 2.000s 38.836us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
uart_csr_rw 1.000s 62.190us 1 1 100.00
uart_csr_aliasing 1.000s 14.119us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
base_random_seq 1 1 100.00
uart_tx_rx 47.000s 22814.017us 1 1 100.00
parity 2 2 100.00
uart_smoke 10.000s 5556.902us 1 1 100.00
uart_tx_rx 47.000s 22814.017us 1 1 100.00
parity_error 2 2 100.00
uart_intr 76.000s 49215.761us 1 1 100.00
uart_rx_parity_err 23.000s 20144.524us 1 1 100.00
watermark 2 2 100.00
uart_tx_rx 47.000s 22814.017us 1 1 100.00
uart_intr 76.000s 49215.761us 1 1 100.00
fifo_full 1 1 100.00
uart_fifo_full 62.000s 90879.908us 1 1 100.00
fifo_overflow 1 1 100.00
uart_fifo_overflow 37.000s 33357.551us 1 1 100.00
fifo_reset 1 1 100.00
uart_fifo_reset 333.000s 126864.154us 1 1 100.00
rx_frame_err 1 1 100.00
uart_intr 76.000s 49215.761us 1 1 100.00
rx_break_err 1 1 100.00
uart_intr 76.000s 49215.761us 1 1 100.00
rx_timeout 1 1 100.00
uart_intr 76.000s 49215.761us 1 1 100.00
perf 1 1 100.00
uart_perf 19.000s 7399.928us 1 1 100.00
sys_loopback 1 1 100.00
uart_loopback 3.000s 9866.403us 1 1 100.00
line_loopback 1 1 100.00
uart_loopback 3.000s 9866.403us 1 1 100.00
rx_noise_filter 1 1 100.00
uart_noise_filter 43.000s 141542.024us 1 1 100.00
rx_start_bit_filter 1 1 100.00
uart_rx_start_bit_filter 19.000s 41362.433us 1 1 100.00
tx_overide 1 1 100.00
uart_tx_ovrd 1.000s 208.548us 1 1 100.00
rx_oversample 1 1 100.00
uart_rx_oversample 7.000s 3700.712us 1 1 100.00
long_b2b_transfer 1 1 100.00
uart_long_xfer_wo_dly 366.000s 39362.558us 1 1 100.00
stress_all 1 1 100.00
uart_stress_all 282.000s 316601.512us 1 1 100.00
alert_test 1 1 100.00
uart_alert_test 1.000s 40.177us 1 1 100.00
intr_test 1 1 100.00
uart_intr_test 2.000s 15.350us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
uart_tl_errors 2.000s 31.172us 1 1 100.00
tl_d_illegal_access 1 1 100.00
uart_tl_errors 2.000s 31.172us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
uart_csr_hw_reset 1.000s 26.627us 1 1 100.00
uart_csr_rw 1.000s 62.190us 1 1 100.00
uart_csr_aliasing 1.000s 14.119us 1 1 100.00
uart_same_csr_outstanding 2.000s 67.376us 1 1 100.00
tl_d_partial_access 4 4 100.00
uart_csr_hw_reset 1.000s 26.627us 1 1 100.00
uart_csr_rw 1.000s 62.190us 1 1 100.00
uart_csr_aliasing 1.000s 14.119us 1 1 100.00
uart_same_csr_outstanding 2.000s 67.376us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
uart_sec_cm 1.000s 752.990us 1 1 100.00
uart_tl_intg_err 2.000s 1207.350us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
uart_tl_intg_err 2.000s 1207.350us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 1 1 100.00
uart_stress_all_with_rand_reset 20.000s 1837.376us 1 1 100.00