Simulation Results: ac_range_check

 
31/08/2026 21:27:41 DVSim: v1.52.0 sha: 93d21e7 json Branch: master Tool: xcelium [24.03-s007]
Coverage statistics
  • Total
  • 82.93 %
  • code
  • 93.12 %
  • assert
  • 97.75 %
  • func
  • 57.93 %
  • block
  • 99.10 %
  • line
  • 99.93 %
  • branch
  • 98.24 %
  • toggle
  • 81.18 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
V3
100.00%
unmapped
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
ac_range_check_smoke 1 1 100.00
ac_range_check_smoke 43.000s 1465.110us 1 1 100.00
ac_range_check_smoke_racl 1 1 100.00
ac_range_check_smoke_racl 52.000s 2887.473us 1 1 100.00
csr_hw_reset 1 1 100.00
ac_range_check_csr_hw_reset 11.000s 90.123us 1 1 100.00
csr_rw 1 1 100.00
ac_range_check_csr_rw 11.000s 53.974us 1 1 100.00
csr_bit_bash 1 1 100.00
ac_range_check_csr_bit_bash 51.000s 3044.970us 1 1 100.00
csr_aliasing 1 1 100.00
ac_range_check_csr_aliasing 14.000s 425.336us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
ac_range_check_csr_mem_rw_with_rand_reset 10.000s 35.920us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
ac_range_check_csr_rw 11.000s 53.974us 1 1 100.00
ac_range_check_csr_aliasing 14.000s 425.336us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
ac_range_check_lock_range 1 1 100.00
ac_range_check_lock_range 11.000s 315.227us 1 1 100.00
ac_range_bypass_enable 1 1 100.00
ac_range_check_bypass 45.000s 1605.508us 1 1 100.00
stress_all 1 1 100.00
ac_range_check_stress_all 250.000s 23306.330us 1 1 100.00
alert_test 1 1 100.00
ac_range_check_alert_test 10.000s 49.742us 1 1 100.00
intr_test 1 1 100.00
ac_range_check_intr_test 10.000s 14.528us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
ac_range_check_tl_errors 10.000s 938.721us 1 1 100.00
tl_d_illegal_access 1 1 100.00
ac_range_check_tl_errors 10.000s 938.721us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
ac_range_check_csr_hw_reset 11.000s 90.123us 1 1 100.00
ac_range_check_csr_rw 11.000s 53.974us 1 1 100.00
ac_range_check_csr_aliasing 14.000s 425.336us 1 1 100.00
ac_range_check_same_csr_outstanding 14.000s 191.131us 1 1 100.00
tl_d_partial_access 4 4 100.00
ac_range_check_csr_hw_reset 11.000s 90.123us 1 1 100.00
ac_range_check_csr_rw 11.000s 53.974us 1 1 100.00
ac_range_check_csr_aliasing 14.000s 425.336us 1 1 100.00
ac_range_check_same_csr_outstanding 14.000s 191.131us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
shadow_reg_update_error 1 1 100.00
ac_range_check_shadow_reg_errors 17.000s 365.500us 1 1 100.00
shadow_reg_read_clear_staged_value 1 1 100.00
ac_range_check_shadow_reg_errors 17.000s 365.500us 1 1 100.00
shadow_reg_storage_error 1 1 100.00
ac_range_check_shadow_reg_errors 17.000s 365.500us 1 1 100.00
shadowed_reset_glitch 1 1 100.00
ac_range_check_shadow_reg_errors 17.000s 365.500us 1 1 100.00
shadow_reg_update_error_with_csr_rw 1 1 100.00
ac_range_check_shadow_reg_errors_with_csr_rw 82.000s 3007.173us 1 1 100.00
tl_intg_err 2 2 100.00
ac_range_check_sec_cm 8.000s 31.505us 1 1 100.00
ac_range_check_tl_intg_err 15.000s 233.335us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 1 1 100.00
ac_range_check_stress_all_with_rand_reset 283.000s 3757.524us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
Unmapped 1 1 100.00
ac_range_check_smoke_high_threshold 32.000s 805.424us 1 1 100.00