Simulation Results: aes/gcm_masked

 
31/08/2026 21:27:41 DVSim: v1.52.0 sha: 93d21e7 json Branch: master Tool: xcelium [24.03-s007]
Coverage statistics
  • Total
  • 86.48 %
  • code
  • 95.85 %
  • assert
  • 98.29 %
  • func
  • 65.29 %
  • block
  • 95.87 %
  • line
  • 97.50 %
  • branch
  • 89.80 %
  • toggle
  • 98.05 %
  • FSM
  • 98.06 %
Validation stages
V1
100.00%
V2
100.00%
V2S
94.44%
V3
0.00%
Testpoint Test Max Runtime Sim Time Pass Total %
wake_up 1 1 100.00
aes_wake_up 2.000s 77.149us 1 1 100.00
smoke 1 1 100.00
aes_smoke 4.000s 122.765us 1 1 100.00
csr_hw_reset 1 1 100.00
aes_csr_hw_reset 2.000s 105.748us 1 1 100.00
csr_rw 1 1 100.00
aes_csr_rw 2.000s 89.963us 1 1 100.00
csr_bit_bash 1 1 100.00
aes_csr_bit_bash 7.000s 246.306us 1 1 100.00
csr_aliasing 1 1 100.00
aes_csr_aliasing 2.000s 75.169us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
aes_csr_mem_rw_with_rand_reset 2.000s 58.014us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
aes_csr_rw 2.000s 89.963us 1 1 100.00
aes_csr_aliasing 2.000s 75.169us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
algorithm 3 3 100.00
aes_smoke 4.000s 122.765us 1 1 100.00
aes_config_error 3.000s 105.057us 1 1 100.00
aes_stress 22.000s 630.416us 1 1 100.00
key_length 3 3 100.00
aes_smoke 4.000s 122.765us 1 1 100.00
aes_config_error 3.000s 105.057us 1 1 100.00
aes_stress 22.000s 630.416us 1 1 100.00
back2back 2 2 100.00
aes_stress 22.000s 630.416us 1 1 100.00
aes_b2b 12.000s 759.449us 1 1 100.00
backpressure 1 1 100.00
aes_stress 22.000s 630.416us 1 1 100.00
multi_message 4 4 100.00
aes_smoke 4.000s 122.765us 1 1 100.00
aes_config_error 3.000s 105.057us 1 1 100.00
aes_stress 22.000s 630.416us 1 1 100.00
aes_alert_reset 3.000s 142.011us 1 1 100.00
failure_test 3 3 100.00
aes_man_cfg_err 2.000s 82.448us 1 1 100.00
aes_config_error 3.000s 105.057us 1 1 100.00
aes_alert_reset 3.000s 142.011us 1 1 100.00
trigger_clear_test 1 1 100.00
aes_clear 3.000s 120.020us 1 1 100.00
nist_test_vectors 1 1 100.00
aes_nist_vectors 8.000s 641.073us 1 1 100.00
nist_test_vectors_gcm 1 1 100.00
aes_nist_vectors_gcm 8.000s 957.397us 1 1 100.00
reset_recovery 1 1 100.00
aes_alert_reset 3.000s 142.011us 1 1 100.00
stress 1 1 100.00
aes_stress 22.000s 630.416us 1 1 100.00
sideload 2 2 100.00
aes_stress 22.000s 630.416us 1 1 100.00
aes_sideload 4.000s 62.612us 1 1 100.00
deinitialization 1 1 100.00
aes_deinit 4.000s 1151.903us 1 1 100.00
stress_all 1 1 100.00
aes_stress_all 20.000s 708.240us 1 1 100.00
gcm_save_and_restore 1 1 100.00
aes_gcm_save_restore 4.000s 79.426us 1 1 100.00
alert_test 1 1 100.00
aes_alert_test 2.000s 335.018us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
aes_tl_errors 2.000s 94.355us 1 1 100.00
tl_d_illegal_access 1 1 100.00
aes_tl_errors 2.000s 94.355us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
aes_csr_hw_reset 2.000s 105.748us 1 1 100.00
aes_csr_rw 2.000s 89.963us 1 1 100.00
aes_csr_aliasing 2.000s 75.169us 1 1 100.00
aes_same_csr_outstanding 2.000s 82.143us 1 1 100.00
tl_d_partial_access 4 4 100.00
aes_csr_hw_reset 2.000s 105.748us 1 1 100.00
aes_csr_rw 2.000s 89.963us 1 1 100.00
aes_csr_aliasing 2.000s 75.169us 1 1 100.00
aes_same_csr_outstanding 2.000s 82.143us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
reseeding 1 1 100.00
aes_reseed 3.000s 546.209us 1 1 100.00
fault_inject 2 3 66.67
aes_fi 8.000s 1057.316us 0 1 0.00
aes_control_fi 2.000s 72.873us 1 1 100.00
aes_cipher_fi 3.000s 65.592us 1 1 100.00
shadow_reg_update_error 1 1 100.00
aes_shadow_reg_errors 2.000s 131.523us 1 1 100.00
shadow_reg_read_clear_staged_value 1 1 100.00
aes_shadow_reg_errors 2.000s 131.523us 1 1 100.00
shadow_reg_storage_error 1 1 100.00
aes_shadow_reg_errors 2.000s 131.523us 1 1 100.00
shadowed_reset_glitch 1 1 100.00
aes_shadow_reg_errors 2.000s 131.523us 1 1 100.00
shadow_reg_update_error_with_csr_rw 1 1 100.00
aes_shadow_reg_errors_with_csr_rw 4.000s 157.054us 1 1 100.00
tl_intg_err 2 2 100.00
aes_sec_cm 5.000s 549.604us 1 1 100.00
aes_tl_intg_err 3.000s 222.681us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
aes_tl_intg_err 3.000s 222.681us 1 1 100.00
sec_cm_lc_escalate_en_intersig_mubi 1 1 100.00
aes_alert_reset 3.000s 142.011us 1 1 100.00
sec_cm_main_config_shadow 1 1 100.00
aes_shadow_reg_errors 2.000s 131.523us 1 1 100.00
sec_cm_gcm_config_shadow 1 1 100.00
aes_shadow_reg_errors 2.000s 131.523us 1 1 100.00
sec_cm_main_config_sparse 4 4 100.00
aes_smoke 4.000s 122.765us 1 1 100.00
aes_stress 22.000s 630.416us 1 1 100.00
aes_alert_reset 3.000s 142.011us 1 1 100.00
aes_core_fi 2.000s 140.885us 1 1 100.00
sec_cm_gcm_config_sparse 4 4 100.00
aes_gcm_save_restore 4.000s 79.426us 1 1 100.00
aes_config_error 3.000s 105.057us 1 1 100.00
aes_stress 22.000s 630.416us 1 1 100.00
aes_core_fi 2.000s 140.885us 1 1 100.00
sec_cm_aux_config_shadow 1 1 100.00
aes_shadow_reg_errors 2.000s 131.523us 1 1 100.00
sec_cm_aux_config_regwen 2 2 100.00
aes_readability 2.000s 161.852us 1 1 100.00
aes_stress 22.000s 630.416us 1 1 100.00
sec_cm_key_sideload 2 2 100.00
aes_stress 22.000s 630.416us 1 1 100.00
aes_sideload 4.000s 62.612us 1 1 100.00
sec_cm_key_sw_unreadable 1 1 100.00
aes_readability 2.000s 161.852us 1 1 100.00
sec_cm_data_reg_sw_unreadable 1 1 100.00
aes_readability 2.000s 161.852us 1 1 100.00
sec_cm_key_sec_wipe 1 1 100.00
aes_readability 2.000s 161.852us 1 1 100.00
sec_cm_iv_config_sec_wipe 1 1 100.00
aes_readability 2.000s 161.852us 1 1 100.00
sec_cm_data_reg_sec_wipe 1 1 100.00
aes_readability 2.000s 161.852us 1 1 100.00
sec_cm_data_reg_key_sca 1 1 100.00
aes_stress 22.000s 630.416us 1 1 100.00
sec_cm_key_masking 1 1 100.00
aes_stress 22.000s 630.416us 1 1 100.00
sec_cm_main_fsm_sparse 0 1 0.00
aes_fi 8.000s 1057.316us 0 1 0.00
sec_cm_main_fsm_redun 3 4 75.00
aes_fi 8.000s 1057.316us 0 1 0.00
aes_control_fi 2.000s 72.873us 1 1 100.00
aes_cipher_fi 3.000s 65.592us 1 1 100.00
aes_ctr_fi 3.000s 94.400us 1 1 100.00
sec_cm_cipher_fsm_sparse 0 1 0.00
aes_fi 8.000s 1057.316us 0 1 0.00
sec_cm_cipher_fsm_redun 2 3 66.67
aes_fi 8.000s 1057.316us 0 1 0.00
aes_control_fi 2.000s 72.873us 1 1 100.00
aes_cipher_fi 3.000s 65.592us 1 1 100.00
sec_cm_cipher_ctr_redun 1 1 100.00
aes_cipher_fi 3.000s 65.592us 1 1 100.00
sec_cm_ctr_fsm_sparse 0 1 0.00
aes_fi 8.000s 1057.316us 0 1 0.00
sec_cm_ctr_fsm_redun 2 3 66.67
aes_fi 8.000s 1057.316us 0 1 0.00
aes_control_fi 2.000s 72.873us 1 1 100.00
aes_ctr_fi 3.000s 94.400us 1 1 100.00
sec_cm_ghash_fsm_sparse 0 1 0.00
aes_fi 8.000s 1057.316us 0 1 0.00
sec_cm_ctrl_sparse 3 4 75.00
aes_fi 8.000s 1057.316us 0 1 0.00
aes_control_fi 2.000s 72.873us 1 1 100.00
aes_cipher_fi 3.000s 65.592us 1 1 100.00
aes_ctr_fi 3.000s 94.400us 1 1 100.00
sec_cm_main_fsm_global_esc 1 1 100.00
aes_alert_reset 3.000s 142.011us 1 1 100.00
sec_cm_main_fsm_local_esc 3 4 75.00
aes_fi 8.000s 1057.316us 0 1 0.00
aes_control_fi 2.000s 72.873us 1 1 100.00
aes_cipher_fi 3.000s 65.592us 1 1 100.00
aes_ctr_fi 3.000s 94.400us 1 1 100.00
sec_cm_cipher_fsm_local_esc 3 4 75.00
aes_fi 8.000s 1057.316us 0 1 0.00
aes_control_fi 2.000s 72.873us 1 1 100.00
aes_cipher_fi 3.000s 65.592us 1 1 100.00
aes_ctr_fi 3.000s 94.400us 1 1 100.00
sec_cm_ctr_fsm_local_esc 2 3 66.67
aes_fi 8.000s 1057.316us 0 1 0.00
aes_control_fi 2.000s 72.873us 1 1 100.00
aes_ctr_fi 3.000s 94.400us 1 1 100.00
sec_cm_ghash_fsm_local_esc 1 2 50.00
aes_ghash_fi 1.000s 48.697us 1 1 100.00
aes_fi 8.000s 1057.316us 0 1 0.00
sec_cm_data_reg_local_esc 2 3 66.67
aes_fi 8.000s 1057.316us 0 1 0.00
aes_control_fi 2.000s 72.873us 1 1 100.00
aes_cipher_fi 3.000s 65.592us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 0 1 0.00
aes_stress_all_with_rand_reset 5.000s 69.310us 0 1 0.00

Error Messages

   Test seed line log context
UVM_FATAL (aes_scoreboard.sv:923) scoreboard [scoreboard] 1 test run
aes_fi 61510105880250639136820584898823452851870256836718000887858753892166240260678 12108
----| NO FAILURES BUT NUMBER OF EXPECTED MESSAGES DOES NOT MATCH ACTUAL
----| Expected: 6
----| Seen: 5
----| Expected corrupted: 0
UVM_ERROR (uvm_sequencer_base.svh:757) sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'sequencer' for sequence 'parent_sequence' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues 1 test run
aes_stress_all_with_rand_reset 96827194238511935105975972713107911362070757782907588295465082960795731403589 188
UVM_INFO @ 69310232 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---