Simulation Results: aes/gcm_unmasked

 
31/08/2026 21:27:41 DVSim: v1.52.0 sha: 93d21e7 json Branch: master Tool: xcelium [24.03-s007]
Coverage statistics
  • Total
  • 83.89 %
  • code
  • 90.91 %
  • assert
  • 97.94 %
  • func
  • 62.81 %
  • block
  • 91.00 %
  • line
  • 92.97 %
  • branch
  • 84.02 %
  • toggle
  • 97.99 %
  • FSM
  • 88.65 %
Validation stages
V1
100.00%
V2
94.12%
V2S
93.75%
V3
0.00%
Testpoint Test Max Runtime Sim Time Pass Total %
wake_up 1 1 100.00
aes_wake_up 2.000s 63.342us 1 1 100.00
smoke 1 1 100.00
aes_smoke 3.000s 226.379us 1 1 100.00
csr_hw_reset 1 1 100.00
aes_csr_hw_reset 2.000s 94.107us 1 1 100.00
csr_rw 1 1 100.00
aes_csr_rw 2.000s 135.737us 1 1 100.00
csr_bit_bash 1 1 100.00
aes_csr_bit_bash 7.000s 268.604us 1 1 100.00
csr_aliasing 1 1 100.00
aes_csr_aliasing 1.000s 97.060us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
aes_csr_mem_rw_with_rand_reset 2.000s 137.681us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
aes_csr_rw 2.000s 135.737us 1 1 100.00
aes_csr_aliasing 1.000s 97.060us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
algorithm 3 3 100.00
aes_smoke 3.000s 226.379us 1 1 100.00
aes_config_error 2.000s 150.790us 1 1 100.00
aes_stress 3.000s 111.988us 1 1 100.00
key_length 3 3 100.00
aes_smoke 3.000s 226.379us 1 1 100.00
aes_config_error 2.000s 150.790us 1 1 100.00
aes_stress 3.000s 111.988us 1 1 100.00
back2back 2 2 100.00
aes_stress 3.000s 111.988us 1 1 100.00
aes_b2b 7.000s 229.365us 1 1 100.00
backpressure 1 1 100.00
aes_stress 3.000s 111.988us 1 1 100.00
multi_message 4 4 100.00
aes_smoke 3.000s 226.379us 1 1 100.00
aes_config_error 2.000s 150.790us 1 1 100.00
aes_stress 3.000s 111.988us 1 1 100.00
aes_alert_reset 3.000s 286.435us 1 1 100.00
failure_test 3 3 100.00
aes_man_cfg_err 2.000s 83.384us 1 1 100.00
aes_config_error 2.000s 150.790us 1 1 100.00
aes_alert_reset 3.000s 286.435us 1 1 100.00
trigger_clear_test 1 1 100.00
aes_clear 2.000s 195.805us 1 1 100.00
nist_test_vectors 1 1 100.00
aes_nist_vectors 4.000s 127.145us 1 1 100.00
reset_recovery 1 1 100.00
aes_alert_reset 3.000s 286.435us 1 1 100.00
stress 1 1 100.00
aes_stress 3.000s 111.988us 1 1 100.00
sideload 2 2 100.00
aes_stress 3.000s 111.988us 1 1 100.00
aes_sideload 3.000s 120.158us 1 1 100.00
deinitialization 1 1 100.00
aes_deinit 3.000s 338.887us 1 1 100.00
stress_all 0 1 0.00
aes_stress_all 10801.000s 0.000us 0 1 0.00
alert_test 1 1 100.00
aes_alert_test 1.000s 99.029us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
aes_tl_errors 4.000s 253.694us 1 1 100.00
tl_d_illegal_access 1 1 100.00
aes_tl_errors 4.000s 253.694us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
aes_csr_hw_reset 2.000s 94.107us 1 1 100.00
aes_csr_rw 2.000s 135.737us 1 1 100.00
aes_csr_aliasing 1.000s 97.060us 1 1 100.00
aes_same_csr_outstanding 2.000s 172.153us 1 1 100.00
tl_d_partial_access 4 4 100.00
aes_csr_hw_reset 2.000s 94.107us 1 1 100.00
aes_csr_rw 2.000s 135.737us 1 1 100.00
aes_csr_aliasing 1.000s 97.060us 1 1 100.00
aes_same_csr_outstanding 2.000s 172.153us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
reseeding 1 1 100.00
aes_reseed 3.000s 66.861us 1 1 100.00
fault_inject 2 3 66.67
aes_fi 2.000s 138.597us 0 1 0.00
aes_control_fi 2.000s 66.057us 1 1 100.00
aes_cipher_fi 2.000s 65.308us 1 1 100.00
shadow_reg_update_error 1 1 100.00
aes_shadow_reg_errors 2.000s 254.897us 1 1 100.00
shadow_reg_read_clear_staged_value 1 1 100.00
aes_shadow_reg_errors 2.000s 254.897us 1 1 100.00
shadow_reg_storage_error 1 1 100.00
aes_shadow_reg_errors 2.000s 254.897us 1 1 100.00
shadowed_reset_glitch 1 1 100.00
aes_shadow_reg_errors 2.000s 254.897us 1 1 100.00
shadow_reg_update_error_with_csr_rw 1 1 100.00
aes_shadow_reg_errors_with_csr_rw 3.000s 194.940us 1 1 100.00
tl_intg_err 2 2 100.00
aes_sec_cm 3.000s 2293.185us 1 1 100.00
aes_tl_intg_err 2.000s 202.247us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
aes_tl_intg_err 2.000s 202.247us 1 1 100.00
sec_cm_lc_escalate_en_intersig_mubi 1 1 100.00
aes_alert_reset 3.000s 286.435us 1 1 100.00
sec_cm_main_config_shadow 1 1 100.00
aes_shadow_reg_errors 2.000s 254.897us 1 1 100.00
sec_cm_gcm_config_shadow 1 1 100.00
aes_shadow_reg_errors 2.000s 254.897us 1 1 100.00
sec_cm_main_config_sparse 4 4 100.00
aes_smoke 3.000s 226.379us 1 1 100.00
aes_stress 3.000s 111.988us 1 1 100.00
aes_alert_reset 3.000s 286.435us 1 1 100.00
aes_core_fi 3.000s 75.853us 1 1 100.00
sec_cm_gcm_config_sparse 3 3 100.00
aes_config_error 2.000s 150.790us 1 1 100.00
aes_stress 3.000s 111.988us 1 1 100.00
aes_core_fi 3.000s 75.853us 1 1 100.00
sec_cm_aux_config_shadow 1 1 100.00
aes_shadow_reg_errors 2.000s 254.897us 1 1 100.00
sec_cm_aux_config_regwen 2 2 100.00
aes_readability 2.000s 95.438us 1 1 100.00
aes_stress 3.000s 111.988us 1 1 100.00
sec_cm_key_sideload 2 2 100.00
aes_stress 3.000s 111.988us 1 1 100.00
aes_sideload 3.000s 120.158us 1 1 100.00
sec_cm_key_sw_unreadable 1 1 100.00
aes_readability 2.000s 95.438us 1 1 100.00
sec_cm_data_reg_sw_unreadable 1 1 100.00
aes_readability 2.000s 95.438us 1 1 100.00
sec_cm_key_sec_wipe 1 1 100.00
aes_readability 2.000s 95.438us 1 1 100.00
sec_cm_iv_config_sec_wipe 1 1 100.00
aes_readability 2.000s 95.438us 1 1 100.00
sec_cm_data_reg_sec_wipe 1 1 100.00
aes_readability 2.000s 95.438us 1 1 100.00
sec_cm_data_reg_key_sca 1 1 100.00
aes_stress 3.000s 111.988us 1 1 100.00
sec_cm_key_masking 1 1 100.00
aes_stress 3.000s 111.988us 1 1 100.00
sec_cm_main_fsm_sparse 0 1 0.00
aes_fi 2.000s 138.597us 0 1 0.00
sec_cm_main_fsm_redun 3 4 75.00
aes_fi 2.000s 138.597us 0 1 0.00
aes_control_fi 2.000s 66.057us 1 1 100.00
aes_cipher_fi 2.000s 65.308us 1 1 100.00
aes_ctr_fi 2.000s 74.682us 1 1 100.00
sec_cm_cipher_fsm_sparse 0 1 0.00
aes_fi 2.000s 138.597us 0 1 0.00
sec_cm_cipher_fsm_redun 2 3 66.67
aes_fi 2.000s 138.597us 0 1 0.00
aes_control_fi 2.000s 66.057us 1 1 100.00
aes_cipher_fi 2.000s 65.308us 1 1 100.00
sec_cm_cipher_ctr_redun 1 1 100.00
aes_cipher_fi 2.000s 65.308us 1 1 100.00
sec_cm_ctr_fsm_sparse 0 1 0.00
aes_fi 2.000s 138.597us 0 1 0.00
sec_cm_ctr_fsm_redun 2 3 66.67
aes_fi 2.000s 138.597us 0 1 0.00
aes_control_fi 2.000s 66.057us 1 1 100.00
aes_ctr_fi 2.000s 74.682us 1 1 100.00
sec_cm_ghash_fsm_sparse 0 1 0.00
aes_fi 2.000s 138.597us 0 1 0.00
sec_cm_ctrl_sparse 3 4 75.00
aes_fi 2.000s 138.597us 0 1 0.00
aes_control_fi 2.000s 66.057us 1 1 100.00
aes_cipher_fi 2.000s 65.308us 1 1 100.00
aes_ctr_fi 2.000s 74.682us 1 1 100.00
sec_cm_main_fsm_global_esc 1 1 100.00
aes_alert_reset 3.000s 286.435us 1 1 100.00
sec_cm_main_fsm_local_esc 3 4 75.00
aes_fi 2.000s 138.597us 0 1 0.00
aes_control_fi 2.000s 66.057us 1 1 100.00
aes_cipher_fi 2.000s 65.308us 1 1 100.00
aes_ctr_fi 2.000s 74.682us 1 1 100.00
sec_cm_cipher_fsm_local_esc 3 4 75.00
aes_fi 2.000s 138.597us 0 1 0.00
aes_control_fi 2.000s 66.057us 1 1 100.00
aes_cipher_fi 2.000s 65.308us 1 1 100.00
aes_ctr_fi 2.000s 74.682us 1 1 100.00
sec_cm_ctr_fsm_local_esc 2 3 66.67
aes_fi 2.000s 138.597us 0 1 0.00
aes_control_fi 2.000s 66.057us 1 1 100.00
aes_ctr_fi 2.000s 74.682us 1 1 100.00
sec_cm_ghash_fsm_local_esc 0 1 0.00
aes_fi 2.000s 138.597us 0 1 0.00
sec_cm_data_reg_local_esc 2 3 66.67
aes_fi 2.000s 138.597us 0 1 0.00
aes_control_fi 2.000s 66.057us 1 1 100.00
aes_cipher_fi 2.000s 65.308us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 0 1 0.00
aes_stress_all_with_rand_reset 12.000s 1352.555us 0 1 0.00

Error Messages

   Test seed line log context
UVM_FATAL (aes_scoreboard.sv:923) scoreboard [scoreboard] 1 test run
aes_fi 55717783554473778710668559669358311804240583517806620412778052653304079642159 5552
----| NO FAILURES BUT NUMBER OF EXPECTED MESSAGES DOES NOT MATCH ACTUAL
----| Expected: 3
----| Seen: 2
----| Expected corrupted: 0
Job timed out after * minutes 1 test run
aes_stress_all 67074631205756342065192556534904199912448670470659409545930689863505939702230 None
UVM_ERROR (uvm_sequencer_base.svh:757) sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'sequencer' for sequence 'parent_sequence' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues 1 test run
aes_stress_all_with_rand_reset 91871436999882772892123424744268256618147473860355834904041104633728687853223 273
UVM_INFO @ 1352555310 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---