Simulation Results: clkmgr

 
31/08/2026 21:27:41 DVSim: v1.52.0 sha: 93d21e7 json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 74.13 %
  • code
  • 68.60 %
  • assert
  • 88.22 %
  • func
  • 65.58 %
  • line
  • 81.81 %
  • branch
  • 86.86 %
  • cond
  • 74.89 %
  • toggle
  • 99.43 %
  • FSM
  • 0.00 %
Validation stages
V1
66.67%
V2
61.54%
V2S
37.50%
V3
0.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
clkmgr_smoke 1.450s 27.393us 1 1 100.00
csr_hw_reset 1 1 100.00
clkmgr_csr_hw_reset 1.340s 35.638us 1 1 100.00
csr_rw 1 1 100.00
clkmgr_csr_rw 1.230s 18.561us 1 1 100.00
csr_bit_bash 0 1 0.00
clkmgr_csr_bit_bash 1.290s 19.275us 0 1 0.00
csr_aliasing 0 1 0.00
clkmgr_csr_aliasing 0.880s 3.224us 0 1 0.00
csr_mem_rw_with_rand_reset 1 1 100.00
clkmgr_csr_mem_rw_with_rand_reset 1.920s 103.646us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 1 2 50.00
clkmgr_csr_rw 1.230s 18.561us 1 1 100.00
clkmgr_csr_aliasing 0.880s 3.224us 0 1 0.00
Testpoint Test Max Runtime Sim Time Pass Total %
peri_enables 1 1 100.00
clkmgr_peri 2.400s 107.005us 1 1 100.00
trans_enables 1 1 100.00
clkmgr_trans 2.500s 100.787us 1 1 100.00
clk_status 1 1 100.00
clkmgr_clk_status 1.450s 50.559us 1 1 100.00
jitter 1 1 100.00
clkmgr_smoke 1.450s 27.393us 1 1 100.00
frequency 0 1 0.00
clkmgr_frequency 0.840s 8.039us 0 1 0.00
frequency_timeout 0 1 0.00
clkmgr_frequency_timeout 0.930s 8.256us 0 1 0.00
frequency_overflow 0 1 0.00
clkmgr_frequency 0.840s 8.039us 0 1 0.00
stress_all 0 1 0.00
clkmgr_stress_all 1.650s 80.387us 0 1 0.00
alert_test 1 1 100.00
clkmgr_alert_test 1.120s 15.549us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
clkmgr_tl_errors 7.850s 435.051us 1 1 100.00
tl_d_illegal_access 1 1 100.00
clkmgr_tl_errors 7.850s 435.051us 1 1 100.00
tl_d_outstanding_access 2 4 50.00
clkmgr_csr_hw_reset 1.340s 35.638us 1 1 100.00
clkmgr_csr_rw 1.230s 18.561us 1 1 100.00
clkmgr_csr_aliasing 0.880s 3.224us 0 1 0.00
clkmgr_same_csr_outstanding 0.910s 6.211us 0 1 0.00
tl_d_partial_access 2 4 50.00
clkmgr_csr_hw_reset 1.340s 35.638us 1 1 100.00
clkmgr_csr_rw 1.230s 18.561us 1 1 100.00
clkmgr_csr_aliasing 0.880s 3.224us 0 1 0.00
clkmgr_same_csr_outstanding 0.910s 6.211us 0 1 0.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 1 2 50.00
clkmgr_sec_cm 4.470s 212.740us 1 1 100.00
clkmgr_tl_intg_err 1.210s 14.224us 0 1 0.00
shadow_reg_update_error 0 1 0.00
clkmgr_shadow_reg_errors 2188.060s 200000.000us 0 1 0.00
shadow_reg_read_clear_staged_value 0 1 0.00
clkmgr_shadow_reg_errors 2188.060s 200000.000us 0 1 0.00
shadow_reg_storage_error 0 1 0.00
clkmgr_shadow_reg_errors 2188.060s 200000.000us 0 1 0.00
shadowed_reset_glitch 0 1 0.00
clkmgr_shadow_reg_errors 2188.060s 200000.000us 0 1 0.00
shadow_reg_update_error_with_csr_rw 0 1 0.00
clkmgr_shadow_reg_errors_with_csr_rw 1.440s 25.977us 0 1 0.00
sec_cm_bus_integrity 0 1 0.00
clkmgr_tl_intg_err 1.210s 14.224us 0 1 0.00
sec_cm_meas_clk_bkgn_chk 0 1 0.00
clkmgr_frequency 0.840s 8.039us 0 1 0.00
sec_cm_timeout_clk_bkgn_chk 0 1 0.00
clkmgr_frequency_timeout 0.930s 8.256us 0 1 0.00
sec_cm_meas_config_shadow 0 1 0.00
clkmgr_shadow_reg_errors 2188.060s 200000.000us 0 1 0.00
sec_cm_idle_intersig_mubi 1 1 100.00
clkmgr_idle_intersig_mubi 1.980s 56.103us 1 1 100.00
sec_cm_jitter_config_mubi 1 1 100.00
clkmgr_csr_rw 1.230s 18.561us 1 1 100.00
sec_cm_idle_ctr_redun 1 1 100.00
clkmgr_sec_cm 4.470s 212.740us 1 1 100.00
sec_cm_meas_config_regwen 1 1 100.00
clkmgr_csr_rw 1.230s 18.561us 1 1 100.00
sec_cm_clk_ctrl_config_regwen 1 1 100.00
clkmgr_csr_rw 1.230s 18.561us 1 1 100.00
prim_count_check 1 1 100.00
clkmgr_sec_cm 4.470s 212.740us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
regwen 0 1 0.00
clkmgr_regwen 0.940s 4.246us 0 1 0.00
stress_all_with_rand_reset 0 1 0.00
clkmgr_stress_all_with_rand_reset 1.050s 5.943us 0 1 0.00

Error Messages

   Test seed line log context
UVM_ERROR (clkmgr_base_vseq.sv:320) virtual_sequencer [clkmgr_frequency_timeout_vseq] Mismatch for timeout recoverable error, expected *b*, got *b* 3 test runs
clkmgr_frequency_timeout 63595647968990432066463718223776862390821758535381199426091028763164189316457 84
UVM_INFO @ 8255894 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
clkmgr_stress_all_with_rand_reset 28213849088066084879652705578057660158886500109860903526340063576205768691927 85
UVM_INFO @ 5943313 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
clkmgr_stress_all 14978896963703796736426156920724813010215559382318022634578536237313564763375 83
UVM_INFO @ 80386643 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (clkmgr_base_vseq.sv:320) virtual_sequencer [clkmgr_frequency_vseq] Mismatch for measurement recoverable error, expected *b*, got *b* 1 test run
clkmgr_frequency 112981150361783885709253761986303953487864785162619037731267733758116836519067 82
UVM_INFO @ 8038713 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (clkmgr_scoreboard.sv:254) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*]) reg name: clkmgr_reg_block.io_meas_ctrl_en 1 test run
clkmgr_regwen 114190554031310833570447787993639773839709464345191978922753581261015786918179 80
UVM_INFO @ 4246255 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue 1 test run
clkmgr_shadow_reg_errors 84870256203889496314583553882321937703848593324146739009004124460959562030675 81
UVM_INFO @ 200000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (csr_utils_pkg.sv:461) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_*] Check failed obs == exp (* [*] vs * [*]) Regname: clkmgr_reg_block.measure_ctrl_regwen reset value: * 1 test run
clkmgr_shadow_reg_errors_with_csr_rw 65647798881330899694706813571155232612267004956013748792070891024515120016988 81
UVM_INFO @ 25977067 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (csr_utils_pkg.sv:461) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_*] Check failed obs == exp (* [*] vs * [*]) Regname: clkmgr_reg_block.measure_ctrl_regwen.en reset value: * 1 test run
clkmgr_tl_intg_err 33692697941431974110031921090759138551665835560974553593330172463594567357076 110
UVM_INFO @ 14224058 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (csr_utils_pkg.sv:461) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_*] Check failed obs == exp (* [*] vs * [*]) Regname: clkmgr_reg_block.measure_ctrl_regwen reset value: * Wrote clkmgr_reg_block.measure_ctrl_regwen[*]: * 1 test run
clkmgr_csr_bit_bash 103801593131758378058136063512970340092840849697401907431664717938154939463603 81
UVM_INFO @ 19275100 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (csr_utils_pkg.sv:461) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_*] Check failed obs == exp (* [*] vs * [*]) Regname: clkmgr_reg_block.io_meas_ctrl_shadowed reset value: * 1 test run
clkmgr_csr_aliasing 77238182025530242325858868655465644247452697506442264248313234528843238043841 83
UVM_INFO @ 3223599 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (cip_base_vseq.sv:660) [clkmgr_common_vseq] Check failed masked_data == exp_data (* [*] vs * [*]) addr * read out mismatch 1 test run
clkmgr_same_csr_outstanding 42947408850194966213837518637128733536579883925484558127268386119222419751824 81
UVM_INFO @ 6210814 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---