Simulation Results: dma

 
31/08/2026 21:27:41 DVSim: v1.52.0 sha: 93d21e7 json Branch: master Tool: xcelium [24.03-s007]
Coverage statistics
  • Total
  • 82.23 %
  • code
  • 90.76 %
  • assert
  • 96.50 %
  • func
  • 59.42 %
  • block
  • 97.38 %
  • line
  • 96.89 %
  • branch
  • 95.83 %
  • toggle
  • 77.37 %
  • FSM
  • 92.96 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
unmapped
66.67%
Testpoint Test Max Runtime Sim Time Pass Total %
dma_memory_smoke 1 1 100.00
dma_memory_smoke 5.000s 552.984us 1 1 100.00
dma_handshake_smoke 1 1 100.00
dma_handshake_smoke 5.000s 357.318us 1 1 100.00
dma_generic_smoke 1 1 100.00
dma_generic_smoke 7.000s 293.487us 1 1 100.00
csr_hw_reset 1 1 100.00
dma_csr_hw_reset 2.000s 22.736us 1 1 100.00
csr_rw 1 1 100.00
dma_csr_rw 1.000s 27.440us 1 1 100.00
csr_bit_bash 1 1 100.00
dma_csr_bit_bash 9.000s 931.234us 1 1 100.00
csr_aliasing 1 1 100.00
dma_csr_aliasing 2.000s 69.913us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
dma_csr_mem_rw_with_rand_reset 1.000s 168.084us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
dma_csr_rw 1.000s 27.440us 1 1 100.00
dma_csr_aliasing 2.000s 69.913us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
dma_memory_region_lock 1 1 100.00
dma_memory_region_lock 30.000s 7358.534us 1 1 100.00
dma_memory_tl_error 1 1 100.00
dma_memory_stress 300.000s 23498.904us 1 1 100.00
dma_handshake_tl_error 1 1 100.00
dma_handshake_stress 84.000s 6095.079us 1 1 100.00
dma_handshake_stress 1 1 100.00
dma_handshake_stress 84.000s 6095.079us 1 1 100.00
dma_memory_stress 1 1 100.00
dma_memory_stress 300.000s 23498.904us 1 1 100.00
dma_generic_stress 1 1 100.00
dma_generic_stress 330.000s 131807.931us 1 1 100.00
dma_handshake_mem_buffer_overflow 1 1 100.00
dma_handshake_stress 84.000s 6095.079us 1 1 100.00
dma_abort 1 1 100.00
dma_abort 5.000s 303.791us 1 1 100.00
dma_stress_all 1 1 100.00
dma_stress_all 220.000s 17372.594us 1 1 100.00
alert_test 1 1 100.00
dma_alert_test 2.000s 37.102us 1 1 100.00
intr_test 1 1 100.00
dma_intr_test 1.000s 12.425us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
dma_tl_errors 2.000s 33.346us 1 1 100.00
tl_d_illegal_access 1 1 100.00
dma_tl_errors 2.000s 33.346us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
dma_csr_hw_reset 2.000s 22.736us 1 1 100.00
dma_csr_rw 1.000s 27.440us 1 1 100.00
dma_csr_aliasing 2.000s 69.913us 1 1 100.00
dma_same_csr_outstanding 2.000s 73.715us 1 1 100.00
tl_d_partial_access 4 4 100.00
dma_csr_hw_reset 2.000s 22.736us 1 1 100.00
dma_csr_rw 1.000s 27.440us 1 1 100.00
dma_csr_aliasing 2.000s 69.913us 1 1 100.00
dma_same_csr_outstanding 2.000s 73.715us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
dma_illegal_addr_range 3 3 100.00
dma_mem_enabled 30.000s 1600.296us 1 1 100.00
dma_generic_stress 330.000s 131807.931us 1 1 100.00
dma_handshake_stress 84.000s 6095.079us 1 1 100.00
dma_config_lock 1 1 100.00
dma_config_lock 9.000s 287.698us 1 1 100.00
tl_intg_err 2 2 100.00
dma_tl_intg_err 5.000s 3197.098us 1 1 100.00
dma_sec_cm 2.000s 12.735us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
Unmapped 2 3 66.67
dma_short_transfer 82.000s 12806.593us 1 1 100.00
dma_longer_transfer 7.000s 1187.359us 1 1 100.00
dma_stress_all_with_rand_reset 4.000s 161.049us 0 1 0.00

Error Messages

   Test seed line log context
UVM_ERROR @ *ps: (cip_base_vseq.sv:1297) [dma_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. 1 test run
dma_stress_all_with_rand_reset 66833146070382729136369220096127728427239230549263109750633557960135951486995 93
UVM_INFO @ 161049377ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---