Simulation Results: edn/edn0

 
31/08/2026 21:27:41 DVSim: v1.52.0 sha: 93d21e7 json Branch: master Tool: xcelium [24.03-s007]
Coverage statistics
  • Total
  • 79.73 %
  • code
  • 92.35 %
  • assert
  • 96.90 %
  • func
  • 49.93 %
  • block
  • 96.08 %
  • line
  • 98.20 %
  • branch
  • 91.39 %
  • toggle
  • 84.45 %
  • FSM
  • 95.35 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
V3
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
edn_smoke 2.000s 58.042us 1 1 100.00
csr_hw_reset 1 1 100.00
edn_csr_hw_reset 1.000s 26.525us 1 1 100.00
csr_rw 1 1 100.00
edn_csr_rw 2.000s 15.910us 1 1 100.00
csr_bit_bash 1 1 100.00
edn_csr_bit_bash 6.000s 544.275us 1 1 100.00
csr_aliasing 1 1 100.00
edn_csr_aliasing 1.000s 40.941us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
edn_csr_mem_rw_with_rand_reset 2.000s 134.331us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
edn_csr_rw 2.000s 15.910us 1 1 100.00
edn_csr_aliasing 1.000s 40.941us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
firmware 1 1 100.00
edn_genbits 1.000s 90.551us 1 1 100.00
csrng_commands 1 1 100.00
edn_genbits 1.000s 90.551us 1 1 100.00
genbits 1 1 100.00
edn_genbits 1.000s 90.551us 1 1 100.00
interrupts 1 1 100.00
edn_intr 1.000s 30.292us 1 1 100.00
alerts 1 1 100.00
edn_alert 2.000s 27.789us 1 1 100.00
errs 1 1 100.00
edn_err 2.000s 32.259us 1 1 100.00
disable 2 2 100.00
edn_disable 2.000s 21.156us 1 1 100.00
edn_disable_auto_req_mode 2.000s 43.525us 1 1 100.00
stress_all 1 1 100.00
edn_stress_all 13.000s 615.615us 1 1 100.00
intr_test 1 1 100.00
edn_intr_test 2.000s 27.011us 1 1 100.00
alert_test 1 1 100.00
edn_alert_test 2.000s 129.052us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
edn_tl_errors 2.000s 33.812us 1 1 100.00
tl_d_illegal_access 1 1 100.00
edn_tl_errors 2.000s 33.812us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
edn_csr_hw_reset 1.000s 26.525us 1 1 100.00
edn_csr_rw 2.000s 15.910us 1 1 100.00
edn_csr_aliasing 1.000s 40.941us 1 1 100.00
edn_same_csr_outstanding 2.000s 103.745us 1 1 100.00
tl_d_partial_access 4 4 100.00
edn_csr_hw_reset 1.000s 26.525us 1 1 100.00
edn_csr_rw 2.000s 15.910us 1 1 100.00
edn_csr_aliasing 1.000s 40.941us 1 1 100.00
edn_same_csr_outstanding 2.000s 103.745us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
edn_sec_cm 14.000s 842.522us 1 1 100.00
edn_tl_intg_err 2.000s 414.841us 1 1 100.00
sec_cm_config_regwen 1 1 100.00
edn_regwen 2.000s 28.572us 1 1 100.00
sec_cm_config_mubi 1 1 100.00
edn_alert 2.000s 27.789us 1 1 100.00
sec_cm_main_sm_fsm_sparse 1 1 100.00
edn_sec_cm 14.000s 842.522us 1 1 100.00
sec_cm_ack_sm_fsm_sparse 1 1 100.00
edn_sec_cm 14.000s 842.522us 1 1 100.00
sec_cm_fifo_ctr_redun 1 1 100.00
edn_sec_cm 14.000s 842.522us 1 1 100.00
sec_cm_ctr_redun 1 1 100.00
edn_sec_cm 14.000s 842.522us 1 1 100.00
sec_cm_main_sm_ctr_local_esc 2 2 100.00
edn_alert 2.000s 27.789us 1 1 100.00
edn_sec_cm 14.000s 842.522us 1 1 100.00
sec_cm_cs_rdata_bus_consistency 1 1 100.00
edn_alert 2.000s 27.789us 1 1 100.00
sec_cm_tile_link_bus_integrity 1 1 100.00
edn_tl_intg_err 2.000s 414.841us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 1 1 100.00
edn_stress_all_with_rand_reset 60.000s 2305.230us 1 1 100.00