Simulation Results: edn/edn1

 
31/08/2026 21:27:41 DVSim: v1.52.0 sha: 93d21e7 json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 86.89 %
  • code
  • 81.97 %
  • assert
  • 98.44 %
  • func
  • 80.25 %
  • line
  • 98.10 %
  • branch
  • 92.64 %
  • cond
  • 88.00 %
  • toggle
  • 86.78 %
  • FSM
  • 44.32 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
V3
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
edn_smoke 1.200s 55.900us 1 1 100.00
csr_hw_reset 1 1 100.00
edn_csr_hw_reset 0.860s 26.225us 1 1 100.00
csr_rw 1 1 100.00
edn_csr_rw 1.010s 24.394us 1 1 100.00
csr_bit_bash 1 1 100.00
edn_csr_bit_bash 2.890s 170.649us 1 1 100.00
csr_aliasing 1 1 100.00
edn_csr_aliasing 0.940s 40.766us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
edn_csr_mem_rw_with_rand_reset 1.000s 23.475us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
edn_csr_rw 1.010s 24.394us 1 1 100.00
edn_csr_aliasing 0.940s 40.766us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
firmware 1 1 100.00
edn_genbits 1.580s 50.507us 1 1 100.00
csrng_commands 1 1 100.00
edn_genbits 1.580s 50.507us 1 1 100.00
genbits 1 1 100.00
edn_genbits 1.580s 50.507us 1 1 100.00
interrupts 1 1 100.00
edn_intr 1.420s 22.144us 1 1 100.00
alerts 1 1 100.00
edn_alert 1.290s 88.437us 1 1 100.00
errs 1 1 100.00
edn_err 1.010s 81.634us 1 1 100.00
disable 2 2 100.00
edn_disable 1.070s 39.291us 1 1 100.00
edn_disable_auto_req_mode 1.220s 110.263us 1 1 100.00
stress_all 1 1 100.00
edn_stress_all 3.050s 1299.591us 1 1 100.00
intr_test 1 1 100.00
edn_intr_test 0.970s 60.491us 1 1 100.00
alert_test 1 1 100.00
edn_alert_test 1.050s 30.954us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
edn_tl_errors 3.390s 205.184us 1 1 100.00
tl_d_illegal_access 1 1 100.00
edn_tl_errors 3.390s 205.184us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
edn_csr_hw_reset 0.860s 26.225us 1 1 100.00
edn_csr_rw 1.010s 24.394us 1 1 100.00
edn_csr_aliasing 0.940s 40.766us 1 1 100.00
edn_same_csr_outstanding 1.270s 35.324us 1 1 100.00
tl_d_partial_access 4 4 100.00
edn_csr_hw_reset 0.860s 26.225us 1 1 100.00
edn_csr_rw 1.010s 24.394us 1 1 100.00
edn_csr_aliasing 0.940s 40.766us 1 1 100.00
edn_same_csr_outstanding 1.270s 35.324us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
edn_sec_cm 3.160s 576.279us 1 1 100.00
edn_tl_intg_err 1.620s 67.253us 1 1 100.00
sec_cm_config_regwen 1 1 100.00
edn_regwen 1.220s 24.757us 1 1 100.00
sec_cm_config_mubi 1 1 100.00
edn_alert 1.290s 88.437us 1 1 100.00
sec_cm_main_sm_fsm_sparse 1 1 100.00
edn_sec_cm 3.160s 576.279us 1 1 100.00
sec_cm_ack_sm_fsm_sparse 1 1 100.00
edn_sec_cm 3.160s 576.279us 1 1 100.00
sec_cm_fifo_ctr_redun 1 1 100.00
edn_sec_cm 3.160s 576.279us 1 1 100.00
sec_cm_ctr_redun 1 1 100.00
edn_sec_cm 3.160s 576.279us 1 1 100.00
sec_cm_main_sm_ctr_local_esc 2 2 100.00
edn_alert 1.290s 88.437us 1 1 100.00
edn_sec_cm 3.160s 576.279us 1 1 100.00
sec_cm_cs_rdata_bus_consistency 1 1 100.00
edn_alert 1.290s 88.437us 1 1 100.00
sec_cm_tile_link_bus_integrity 1 1 100.00
edn_tl_intg_err 1.620s 67.253us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 1 1 100.00
edn_stress_all_with_rand_reset 41.900s 2010.710us 1 1 100.00