Simulation Results: entropy_src/rng_16bits

 
31/08/2026 21:27:41 DVSim: v1.52.0 sha: 93d21e7 json Branch: master Tool: xcelium [24.03-s007]
Coverage statistics
  • Total
  • 71.43 %
  • code
  • 83.42 %
  • assert
  • 73.78 %
  • func
  • 57.09 %
  • block
  • 94.19 %
  • line
  • 97.88 %
  • branch
  • 86.29 %
  • toggle
  • 52.62 %
  • FSM
  • 96.88 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
V3
50.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
entropy_src_smoke 3.000s 20.117us 1 1 100.00
csr_hw_reset 1 1 100.00
entropy_src_csr_hw_reset 2.000s 97.981us 1 1 100.00
csr_rw 1 1 100.00
entropy_src_csr_rw 2.000s 75.890us 1 1 100.00
csr_bit_bash 1 1 100.00
entropy_src_csr_bit_bash 11.000s 231.590us 1 1 100.00
csr_aliasing 1 1 100.00
entropy_src_csr_aliasing 2.000s 26.083us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
entropy_src_csr_mem_rw_with_rand_reset 3.000s 73.975us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
entropy_src_csr_rw 2.000s 75.890us 1 1 100.00
entropy_src_csr_aliasing 2.000s 26.083us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
firmware 3 3 100.00
entropy_src_smoke 3.000s 20.117us 1 1 100.00
entropy_src_rng 130.000s 14038.151us 1 1 100.00
entropy_src_fw_ov 145.000s 14144.169us 1 1 100.00
firmware_mode 1 1 100.00
entropy_src_fw_ov 145.000s 14144.169us 1 1 100.00
rng_mode 1 1 100.00
entropy_src_rng 130.000s 14038.151us 1 1 100.00
rng_max_rate 1 1 100.00
entropy_src_rng_max_rate 424.000s 13027.547us 1 1 100.00
health_checks 1 1 100.00
entropy_src_rng 130.000s 14038.151us 1 1 100.00
conditioning 1 1 100.00
entropy_src_rng 130.000s 14038.151us 1 1 100.00
interrupts 2 2 100.00
entropy_src_rng 130.000s 14038.151us 1 1 100.00
entropy_src_intr 34.000s 3536.875us 1 1 100.00
alerts 2 2 100.00
entropy_src_rng 130.000s 14038.151us 1 1 100.00
entropy_src_functional_alerts 9.000s 354.393us 1 1 100.00
stress_all 1 1 100.00
entropy_src_stress_all 239.000s 14215.743us 1 1 100.00
functional_errors 1 1 100.00
entropy_src_functional_errors 3.000s 30.916us 1 1 100.00
firmware_ov_read_contiguous_data 1 1 100.00
entropy_src_fw_ov_contiguous 6.000s 78.137us 1 1 100.00
intr_test 1 1 100.00
entropy_src_intr_test 2.000s 114.413us 1 1 100.00
alert_test 1 1 100.00
entropy_src_alert_test 2.000s 64.645us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
entropy_src_tl_errors 4.000s 49.793us 1 1 100.00
tl_d_illegal_access 1 1 100.00
entropy_src_tl_errors 4.000s 49.793us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
entropy_src_csr_hw_reset 2.000s 97.981us 1 1 100.00
entropy_src_csr_rw 2.000s 75.890us 1 1 100.00
entropy_src_csr_aliasing 2.000s 26.083us 1 1 100.00
entropy_src_same_csr_outstanding 3.000s 399.993us 1 1 100.00
tl_d_partial_access 4 4 100.00
entropy_src_csr_hw_reset 2.000s 97.981us 1 1 100.00
entropy_src_csr_rw 2.000s 75.890us 1 1 100.00
entropy_src_csr_aliasing 2.000s 26.083us 1 1 100.00
entropy_src_same_csr_outstanding 3.000s 399.993us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
entropy_src_sec_cm 3.000s 94.073us 1 1 100.00
entropy_src_tl_intg_err 3.000s 68.470us 1 1 100.00
sec_cm_config_regwen 2 2 100.00
entropy_src_rng 130.000s 14038.151us 1 1 100.00
entropy_src_cfg_regwen 2.000s 16.849us 1 1 100.00
sec_cm_config_mubi 1 1 100.00
entropy_src_rng 130.000s 14038.151us 1 1 100.00
sec_cm_config_redun 1 1 100.00
entropy_src_rng 130.000s 14038.151us 1 1 100.00
sec_cm_intersig_mubi 2 2 100.00
entropy_src_rng 130.000s 14038.151us 1 1 100.00
entropy_src_fw_ov 145.000s 14144.169us 1 1 100.00
sec_cm_main_sm_fsm_sparse 2 2 100.00
entropy_src_functional_errors 3.000s 30.916us 1 1 100.00
entropy_src_sec_cm 3.000s 94.073us 1 1 100.00
sec_cm_ack_sm_fsm_sparse 2 2 100.00
entropy_src_functional_errors 3.000s 30.916us 1 1 100.00
entropy_src_sec_cm 3.000s 94.073us 1 1 100.00
sec_cm_rng_bkgn_chk 1 1 100.00
entropy_src_rng 130.000s 14038.151us 1 1 100.00
sec_cm_fifo_ctr_redun 2 2 100.00
entropy_src_functional_errors 3.000s 30.916us 1 1 100.00
entropy_src_sec_cm 3.000s 94.073us 1 1 100.00
sec_cm_ctr_redun 2 2 100.00
entropy_src_functional_errors 3.000s 30.916us 1 1 100.00
entropy_src_sec_cm 3.000s 94.073us 1 1 100.00
sec_cm_ctr_local_esc 1 1 100.00
entropy_src_functional_errors 3.000s 30.916us 1 1 100.00
sec_cm_esfinal_rdata_bus_consistency 1 1 100.00
entropy_src_functional_alerts 9.000s 354.393us 1 1 100.00
sec_cm_tile_link_bus_integrity 1 1 100.00
entropy_src_tl_intg_err 3.000s 68.470us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
external_health_tests 1 1 100.00
entropy_src_rng_with_xht_rsps 455.000s 14090.611us 1 1 100.00
stress_all_with_rand_reset 0 1 0.00
entropy_src_stress_all_with_rand_reset 10.000s 232.498us 0 1 0.00

Error Messages

   Test seed line log context
UVM_FATAL (entropy_src_scoreboard.sv:1661) scoreboard [scoreboard] invalid csr: entropy_src_reg_block.extht_hi_threshold 1 test run
entropy_src_stress_all_with_rand_reset 15498692020047524568751351206600801227042552120231937479791898608911871886598 117
UVM_INFO @ 232497770 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---