Simulation Results: hmac

 
31/08/2026 21:27:41 DVSim: v1.52.0 sha: 93d21e7 json Branch: master Tool: xcelium [24.03-s007]
Coverage statistics
  • Total
  • 69.54 %
  • code
  • 83.19 %
  • assert
  • 96.74 %
  • func
  • 28.70 %
  • block
  • 97.46 %
  • line
  • 98.39 %
  • branch
  • 93.64 %
  • toggle
  • 45.89 %
  • FSM
  • 94.83 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
V3
100.00%
unmapped
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
hmac_smoke 14.000s 4523.906us 1 1 100.00
csr_hw_reset 1 1 100.00
hmac_csr_hw_reset 1.000s 23.048us 1 1 100.00
csr_rw 1 1 100.00
hmac_csr_rw 2.000s 60.319us 1 1 100.00
csr_bit_bash 1 1 100.00
hmac_csr_bit_bash 13.000s 1218.882us 1 1 100.00
csr_aliasing 1 1 100.00
hmac_csr_aliasing 1.000s 209.496us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
hmac_csr_mem_rw_with_rand_reset 2.000s 31.534us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
hmac_csr_rw 2.000s 60.319us 1 1 100.00
hmac_csr_aliasing 1.000s 209.496us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
long_msg 1 1 100.00
hmac_long_msg 129.000s 91192.534us 1 1 100.00
back_pressure 1 1 100.00
hmac_back_pressure 19.000s 2133.064us 1 1 100.00
test_vectors 6 6 100.00
hmac_test_sha256_vectors 15.000s 329.221us 1 1 100.00
hmac_test_sha384_vectors 32.000s 1157.962us 1 1 100.00
hmac_test_sha512_vectors 450.000s 14346.477us 1 1 100.00
hmac_test_hmac256_vectors 18.000s 855.474us 1 1 100.00
hmac_test_hmac384_vectors 9.000s 1037.854us 1 1 100.00
hmac_test_hmac512_vectors 19.000s 859.923us 1 1 100.00
burst_wr 1 1 100.00
hmac_burst_wr 25.000s 2051.595us 1 1 100.00
datapath_stress 1 1 100.00
hmac_datapath_stress 363.000s 37816.005us 1 1 100.00
error 1 1 100.00
hmac_error 37.000s 2601.643us 1 1 100.00
wipe_secret 1 1 100.00
hmac_wipe_secret 75.000s 7852.307us 1 1 100.00
save_and_restore 6 6 100.00
hmac_smoke 14.000s 4523.906us 1 1 100.00
hmac_long_msg 129.000s 91192.534us 1 1 100.00
hmac_back_pressure 19.000s 2133.064us 1 1 100.00
hmac_datapath_stress 363.000s 37816.005us 1 1 100.00
hmac_burst_wr 25.000s 2051.595us 1 1 100.00
hmac_stress_all 414.000s 64365.081us 1 1 100.00
fifo_empty_status_interrupt 11 11 100.00
hmac_smoke 14.000s 4523.906us 1 1 100.00
hmac_long_msg 129.000s 91192.534us 1 1 100.00
hmac_back_pressure 19.000s 2133.064us 1 1 100.00
hmac_datapath_stress 363.000s 37816.005us 1 1 100.00
hmac_wipe_secret 75.000s 7852.307us 1 1 100.00
hmac_test_sha256_vectors 15.000s 329.221us 1 1 100.00
hmac_test_sha384_vectors 32.000s 1157.962us 1 1 100.00
hmac_test_sha512_vectors 450.000s 14346.477us 1 1 100.00
hmac_test_hmac256_vectors 18.000s 855.474us 1 1 100.00
hmac_test_hmac384_vectors 9.000s 1037.854us 1 1 100.00
hmac_test_hmac512_vectors 19.000s 859.923us 1 1 100.00
wide_digest_configurable_key_length 14 14 100.00
hmac_smoke 14.000s 4523.906us 1 1 100.00
hmac_long_msg 129.000s 91192.534us 1 1 100.00
hmac_back_pressure 19.000s 2133.064us 1 1 100.00
hmac_datapath_stress 363.000s 37816.005us 1 1 100.00
hmac_burst_wr 25.000s 2051.595us 1 1 100.00
hmac_error 37.000s 2601.643us 1 1 100.00
hmac_wipe_secret 75.000s 7852.307us 1 1 100.00
hmac_test_sha256_vectors 15.000s 329.221us 1 1 100.00
hmac_test_sha384_vectors 32.000s 1157.962us 1 1 100.00
hmac_test_sha512_vectors 450.000s 14346.477us 1 1 100.00
hmac_test_hmac256_vectors 18.000s 855.474us 1 1 100.00
hmac_test_hmac384_vectors 9.000s 1037.854us 1 1 100.00
hmac_test_hmac512_vectors 19.000s 859.923us 1 1 100.00
hmac_stress_all 414.000s 64365.081us 1 1 100.00
stress_all 1 1 100.00
hmac_stress_all 414.000s 64365.081us 1 1 100.00
alert_test 1 1 100.00
hmac_alert_test 2.000s 40.843us 1 1 100.00
intr_test 1 1 100.00
hmac_intr_test 1.000s 35.529us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
hmac_tl_errors 3.000s 567.243us 1 1 100.00
tl_d_illegal_access 1 1 100.00
hmac_tl_errors 3.000s 567.243us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
hmac_csr_hw_reset 1.000s 23.048us 1 1 100.00
hmac_csr_rw 2.000s 60.319us 1 1 100.00
hmac_csr_aliasing 1.000s 209.496us 1 1 100.00
hmac_same_csr_outstanding 4.000s 127.801us 1 1 100.00
tl_d_partial_access 4 4 100.00
hmac_csr_hw_reset 1.000s 23.048us 1 1 100.00
hmac_csr_rw 2.000s 60.319us 1 1 100.00
hmac_csr_aliasing 1.000s 209.496us 1 1 100.00
hmac_same_csr_outstanding 4.000s 127.801us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
hmac_sec_cm 1.000s 254.781us 1 1 100.00
hmac_tl_intg_err 3.000s 139.459us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
hmac_tl_intg_err 3.000s 139.459us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
write_config_and_secret_key_during_msg_wr 1 1 100.00
hmac_smoke 14.000s 4523.906us 1 1 100.00
stress_reset 1 1 100.00
hmac_stress_reset 3.000s 99.255us 1 1 100.00
stress_all_with_rand_reset 1 1 100.00
hmac_stress_all_with_rand_reset 80.000s 3134.329us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
Unmapped 1 1 100.00
hmac_directed 3.000s 194.580us 1 1 100.00