Simulation Results

Simulation Results: i2c

31/08/2026 21:27:41 DVSim: v1.52.0 sha: 93d21e7 json Branch: master Tool: xcelium [24.03-s007]

Coverage statistics

Total
88.17 %

code
86.44 %

assert
96.19 %

func
81.88 %

block
96.25 %

line
95.62 %

branch
93.29 %

toggle
72.68 %

FSM
84.17 %

Validation stages

V1		100.00%
V2		82.93%
V2S		100.00%
V3		0.00%

7/7 passed

100.00 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
host_smoke				1	1	100.00
	i2c_host_smoke	81.000s	1212.042us	1	1	100.00
target_smoke				1	1	100.00
	i2c_target_smoke	10.000s	638.595us	1	1	100.00
csr_hw_reset				1	1	100.00
	i2c_csr_hw_reset	1.000s	26.538us	1	1	100.00
csr_rw				1	1	100.00
	i2c_csr_rw	2.000s	18.217us	1	1	100.00
csr_bit_bash				1	1	100.00
	i2c_csr_bit_bash	4.000s	675.545us	1	1	100.00
csr_aliasing				1	1	100.00
	i2c_csr_aliasing	2.000s	28.586us	1	1	100.00
csr_mem_rw_with_rand_reset				1	1	100.00
	i2c_csr_mem_rw_with_rand_reset	2.000s	70.786us	1	1	100.00
regwen_csr_and_corresponding_lockable_csr				2	2	100.00
	i2c_csr_rw	2.000s	18.217us	1	1	100.00
	i2c_csr_aliasing	2.000s	28.586us	1	1	100.00

34/41 passed

82.93 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
host_error_intr				1	1	100.00
	i2c_host_error_intr	3.000s	166.322us	1	1	100.00
host_stress_all				0	1	0.00
	i2c_host_stress_all	3601.000s	0.000us	0	1	0.00
host_maxperf				0	1	0.00
	i2c_host_perf	3602.216s	0.000us	0	1	0.00
host_override				1	1	100.00
	i2c_host_override	2.000s	29.531us	1	1	100.00
host_fifo_watermark				0	1	0.00
	i2c_host_fifo_watermark	3602.272s	0.000us	0	1	0.00
host_fifo_overflow				1	1	100.00
	i2c_host_fifo_overflow	2548.000s	2546.168us	1	1	100.00
host_fifo_reset				3	3	100.00
	i2c_host_fifo_reset_fmt	2.000s	336.623us	1	1	100.00
	i2c_host_fifo_fmt_empty	36.000s	1677.494us	1	1	100.00
	i2c_host_fifo_reset_rx	5.000s	139.463us	1	1	100.00
host_fifo_full				1	1	100.00
	i2c_host_fifo_full	1598.000s	19007.310us	1	1	100.00
host_timeout				1	1	100.00
	i2c_host_stretch_timeout	31.000s	701.472us	1	1	100.00
i2c_host_mode_toggle				0	1	0.00
	i2c_host_mode_toggle	2.000s	3.783us	0	1	0.00
target_glitch				0	1	0.00
	i2c_target_glitch	5.000s	5566.942us	0	1	0.00
target_stress_all				0	1	0.00
	i2c_target_stress_all	3601.000s	0.000us	0	1	0.00
target_maxperf				1	1	100.00
	i2c_target_perf	4.000s	401.818us	1	1	100.00
target_fifo_empty				2	2	100.00
	i2c_target_stress_rd	17.000s	3549.390us	1	1	100.00
	i2c_target_intr_smoke	8.000s	3548.595us	1	1	100.00
target_fifo_reset				2	2	100.00
	i2c_target_fifo_reset_acq	2.000s	119.343us	1	1	100.00
	i2c_target_fifo_reset_tx	1.000s	424.930us	1	1	100.00
target_fifo_full				2	3	66.67
	i2c_target_stress_wr	3600.000s	0.000us	0	1	0.00
	i2c_target_stress_rd	17.000s	3549.390us	1	1	100.00
	i2c_target_intr_stress_wr	337.000s	10999.136us	1	1	100.00
target_timeout				1	1	100.00
	i2c_target_timeout	10.000s	2161.535us	1	1	100.00
target_clock_stretch				1	1	100.00
	i2c_target_stretch	7.000s	1931.164us	1	1	100.00
bad_address				1	1	100.00
	i2c_target_bad_addr	9.000s	13295.231us	1	1	100.00
target_mode_glitch				1	1	100.00
	i2c_target_hrst	4.000s	921.741us	1	1	100.00
target_fifo_watermark				2	2	100.00
	i2c_target_fifo_watermarks_acq	3.000s	1390.064us	1	1	100.00
	i2c_target_fifo_watermarks_tx	2.000s	78.229us	1	1	100.00
host_mode_config_perf				1	2	50.00
	i2c_host_perf	3602.216s	0.000us	0	1	0.00
	i2c_host_perf_precise	69.000s	2459.685us	1	1	100.00
host_mode_clock_stretching				1	1	100.00
	i2c_host_stretch_timeout	31.000s	701.472us	1	1	100.00
target_mode_tx_stretch_ctrl				1	1	100.00
	i2c_target_tx_stretch_ctrl	3.000s	82.018us	1	1	100.00
target_mode_nack_generation				3	3	100.00
	i2c_target_nack_acqfull	4.000s	1095.291us	1	1	100.00
	i2c_target_nack_acqfull_addr	5.000s	620.783us	1	1	100.00
	i2c_target_nack_txstretch	3.000s	126.080us	1	1	100.00
host_mode_halt_on_nak				1	1	100.00
	i2c_host_may_nack	21.000s	2497.624us	1	1	100.00
target_mode_smbus_maxlen				1	1	100.00
	i2c_target_smbus_maxlen	4.000s	1864.638us	1	1	100.00
alert_test				1	1	100.00
	i2c_alert_test	1.000s	40.953us	1	1	100.00
intr_test				1	1	100.00
	i2c_intr_test	1.000s	33.021us	1	1	100.00
tl_d_oob_addr_access				1	1	100.00
	i2c_tl_errors	2.000s	43.674us	1	1	100.00
tl_d_illegal_access				1	1	100.00
	i2c_tl_errors	2.000s	43.674us	1	1	100.00
tl_d_outstanding_access				4	4	100.00
	i2c_csr_hw_reset	1.000s	26.538us	1	1	100.00
	i2c_csr_rw	2.000s	18.217us	1	1	100.00
	i2c_csr_aliasing	2.000s	28.586us	1	1	100.00
	i2c_same_csr_outstanding	2.000s	35.550us	1	1	100.00
tl_d_partial_access				4	4	100.00
	i2c_csr_hw_reset	1.000s	26.538us	1	1	100.00
	i2c_csr_rw	2.000s	18.217us	1	1	100.00
	i2c_csr_aliasing	2.000s	28.586us	1	1	100.00
	i2c_same_csr_outstanding	2.000s	35.550us	1	1	100.00

V2S

2/2 passed

100.00 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
tl_intg_err				2	2	100.00
	i2c_tl_intg_err	4.000s	305.746us	1	1	100.00
	i2c_sec_cm	2.000s	66.676us	1	1	100.00
sec_cm_bus_integrity				1	1	100.00
	i2c_tl_intg_err	4.000s	305.746us	1	1	100.00

0/3 passed

0.00 %

Testpoint	Test	Max Runtime	Sim Time	Total
host_stress_all_with_rand_reset				1
	i2c_host_stress_all_with_rand_reset	11.000s	1616.322us	1
target_error_intr				1
	i2c_target_unexp_stop	2.000s	143.755us	1
target_stress_all_with_rand_reset				1
	i2c_target_stress_all_with_rand_reset	5.000s	404.963us	1

Error Messages

	Test	seed	line	log context
Job timed out after * minutes				5 test runs
	i2c_host_fifo_watermark	64847829144841225981549328504513033241086556185212041655798573725130393201064	None
	i2c_host_perf	14204833447774306443431403118345002184552740642743649631839919062762405239888	None
	i2c_host_stress_all	11307764189608582969974761930740388873045594253959035616178209796150202232080	None
	i2c_target_stress_wr	18537619571203608960236457793153278876095528182876021458365987383641674157069	None
	i2c_target_stress_all	97803206196763889422915757207701866283729828724581525794699712998404753567216	None
UVM_ERROR (cip_base_vseq.sv:1297) [i2c_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses.				2 test runs
	i2c_host_stress_all_with_rand_reset	96155874698113578663917878586800446070308380864307706837993708242845401230027	94	UVM_INFO @ 1616321586 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	i2c_target_stress_all_with_rand_reset	31262945040690275344047179886176459593358365437757661681416122103120298265826	92	UVM_INFO @ 404963295 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_ERROR sequencer [sequencer] get_next_item/try_next_item called twice without item_done or get in between				1 test run
	i2c_target_glitch	44753386105688091058322198301533323389377078922613277765974236101701646922434	93	UVM_INFO @ 5566942384 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_ERROR (i2c_scoreboard.sv:680) [scoreboard] Check failed obs.data_q[i] == exp.data_q[i] (* [] vs [*])				1 test run
	i2c_target_unexp_stop	102249375216161718365695251370547608789351496955332586647310263299873406329694	87	UVM_INFO @ 143754907 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_ERROR sequencer [sequencer] Get_next_item called twice without item_done or get in between				1 test run
	i2c_host_mode_toggle	44474327568446814590932799204460530622225689390541229232737325153452956363085	90	UVM_INFO @ 3783337 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---