Simulation Results

Simulation Results: keymgr_dpe/darjeeling

31/08/2026 21:27:41 DVSim: v1.52.0 sha: 93d21e7 json Branch: master Tool: xcelium [24.03-s007]

Coverage statistics

Total
65.57 %

code
82.44 %

assert
96.96 %

func
17.32 %

block
97.91 %

line
98.64 %

branch
93.22 %

toggle
56.37 %

FSM
81.54 %

Validation stages

V1		100.00%
V2		100.00%
V2S		100.00%

V1

6/6 passed

100.00 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
smoke				1	1	100.00
	keymgr_dpe_smoke	20.000s	1184.800us	1	1	100.00
csr_hw_reset				1	1	100.00
	keymgr_dpe_csr_hw_reset	1.000s	72.653us	1	1	100.00
csr_rw				1	1	100.00
	keymgr_dpe_csr_rw	2.000s	12.529us	1	1	100.00
csr_bit_bash				1	1	100.00
	keymgr_dpe_csr_bit_bash	7.000s	1752.820us	1	1	100.00
csr_aliasing				1	1	100.00
	keymgr_dpe_csr_aliasing	2.000s	198.897us	1	1	100.00
csr_mem_rw_with_rand_reset				1	1	100.00
	keymgr_dpe_csr_mem_rw_with_rand_reset	2.000s	18.943us	1	1	100.00
regwen_csr_and_corresponding_lockable_csr				2	2	100.00
	keymgr_dpe_csr_rw	2.000s	12.529us	1	1	100.00
	keymgr_dpe_csr_aliasing	2.000s	198.897us	1	1	100.00

V2

7/7 passed

100.00 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
intr_test				1	1	100.00
	keymgr_dpe_intr_test	2.000s	71.962us	1	1	100.00
alert_test				1	1	100.00
	keymgr_dpe_alert_test	2.000s	60.878us	1	1	100.00
tl_d_oob_addr_access				1	1	100.00
	keymgr_dpe_tl_errors	2.000s	796.636us	1	1	100.00
tl_d_illegal_access				1	1	100.00
	keymgr_dpe_tl_errors	2.000s	796.636us	1	1	100.00
tl_d_outstanding_access				4	4	100.00
	keymgr_dpe_csr_hw_reset	1.000s	72.653us	1	1	100.00
	keymgr_dpe_csr_rw	2.000s	12.529us	1	1	100.00
	keymgr_dpe_csr_aliasing	2.000s	198.897us	1	1	100.00
	keymgr_dpe_same_csr_outstanding	2.000s	36.024us	1	1	100.00
tl_d_partial_access				4	4	100.00
	keymgr_dpe_csr_hw_reset	1.000s	72.653us	1	1	100.00
	keymgr_dpe_csr_rw	2.000s	12.529us	1	1	100.00
	keymgr_dpe_csr_aliasing	2.000s	198.897us	1	1	100.00
	keymgr_dpe_same_csr_outstanding	2.000s	36.024us	1	1	100.00

V2S

4/4 passed

100.00 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
tl_intg_err				2	2	100.00
	keymgr_dpe_sec_cm	11.000s	1172.221us	1	1	100.00
	keymgr_dpe_tl_intg_err	4.000s	106.301us	1	1	100.00
shadow_reg_update_error				1	1	100.00
	keymgr_dpe_shadow_reg_errors	2.000s	99.776us	1	1	100.00
shadow_reg_read_clear_staged_value				1	1	100.00
	keymgr_dpe_shadow_reg_errors	2.000s	99.776us	1	1	100.00
shadow_reg_storage_error				1	1	100.00
	keymgr_dpe_shadow_reg_errors	2.000s	99.776us	1	1	100.00
shadowed_reset_glitch				1	1	100.00
	keymgr_dpe_shadow_reg_errors	2.000s	99.776us	1	1	100.00
shadow_reg_update_error_with_csr_rw				1	1	100.00
	keymgr_dpe_shadow_reg_errors_with_csr_rw	4.000s	937.989us	1	1	100.00
prim_count_check				1	1	100.00
	keymgr_dpe_sec_cm	11.000s	1172.221us	1	1	100.00
prim_fsm_check				1	1	100.00
	keymgr_dpe_sec_cm	11.000s	1172.221us	1	1	100.00