Simulation Results: lc_ctrl/volatile_unlock_disabled

 
31/08/2026 21:27:41 DVSim: v1.52.0 sha: 93d21e7 json Branch: master Tool: xcelium [24.03-s007]
Coverage statistics
  • Total
  • 87.61 %
  • code
  • 88.54 %
  • assert
  • 96.54 %
  • func
  • 77.74 %
  • block
  • 95.53 %
  • line
  • 95.88 %
  • branch
  • 88.62 %
  • toggle
  • 79.18 %
  • FSM
  • 90.48 %
Validation stages
V1
100.00%
V2
70.00%
V2S
60.00%
V3
0.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
lc_ctrl_smoke 2.000s 20.855us 1 1 100.00
csr_hw_reset 1 1 100.00
lc_ctrl_csr_hw_reset 2.000s 98.983us 1 1 100.00
csr_rw 1 1 100.00
lc_ctrl_csr_rw 2.000s 69.447us 1 1 100.00
csr_bit_bash 1 1 100.00
lc_ctrl_csr_bit_bash 4.000s 131.641us 1 1 100.00
csr_aliasing 1 1 100.00
lc_ctrl_csr_aliasing 2.000s 23.987us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
lc_ctrl_csr_mem_rw_with_rand_reset 2.000s 25.686us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
lc_ctrl_csr_rw 2.000s 69.447us 1 1 100.00
lc_ctrl_csr_aliasing 2.000s 23.987us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
state_post_trans 0 1 0.00
lc_ctrl_state_post_trans 3600.000s 0.000us 0 1 0.00
regwen_during_op 1 1 100.00
lc_ctrl_regwen_during_op 6.000s 379.253us 1 1 100.00
rand_wr_claim_transition_if 1 1 100.00
lc_ctrl_claim_transition_if 7.000s 13.946us 1 1 100.00
lc_prog_failure 0 1 0.00
lc_ctrl_prog_failure 3601.000s 0.000us 0 1 0.00
lc_state_failure 0 1 0.00
lc_ctrl_state_failure 3601.000s 0.000us 0 1 0.00
lc_errors 0 1 0.00
lc_ctrl_errors 3601.000s 0.000us 0 1 0.00
security_escalation 1 7 14.29
lc_ctrl_state_failure 3601.000s 0.000us 0 1 0.00
lc_ctrl_prog_failure 3601.000s 0.000us 0 1 0.00
lc_ctrl_errors 3601.000s 0.000us 0 1 0.00
lc_ctrl_security_escalation 6.000s 1103.036us 1 1 100.00
lc_ctrl_jtag_state_failure 3600.000s 0.000us 0 1 0.00
lc_ctrl_jtag_prog_failure 3600.000s 0.000us 0 1 0.00
lc_ctrl_jtag_errors 3600.000s 0.000us 0 1 0.00
jtag_access 10 13 76.92
lc_ctrl_jtag_smoke 3.000s 626.353us 1 1 100.00
lc_ctrl_jtag_state_post_trans 3600.000s 0.000us 0 1 0.00
lc_ctrl_jtag_prog_failure 3600.000s 0.000us 0 1 0.00
lc_ctrl_jtag_errors 3600.000s 0.000us 0 1 0.00
lc_ctrl_jtag_access 3.000s 196.432us 1 1 100.00
lc_ctrl_jtag_regwen_during_op 11.000s 946.409us 1 1 100.00
lc_ctrl_jtag_csr_hw_reset 2.000s 59.130us 1 1 100.00
lc_ctrl_jtag_csr_rw 2.000s 416.047us 1 1 100.00
lc_ctrl_jtag_csr_bit_bash 10.000s 752.843us 1 1 100.00
lc_ctrl_jtag_csr_aliasing 2.000s 790.428us 1 1 100.00
lc_ctrl_jtag_same_csr_outstanding 2.000s 66.823us 1 1 100.00
lc_ctrl_jtag_csr_mem_rw_with_rand_reset 4.000s 647.968us 1 1 100.00
lc_ctrl_jtag_alert_test 2.000s 23.145us 1 1 100.00
jtag_priority 1 1 100.00
lc_ctrl_jtag_priority 9.000s 4623.052us 1 1 100.00
lc_ctrl_volatile_unlock 1 1 100.00
lc_ctrl_volatile_unlock_smoke 1.000s 58.911us 1 1 100.00
stress_all 0 1 0.00
lc_ctrl_stress_all 10802.082s 0.000us 0 1 0.00
alert_test 1 1 100.00
lc_ctrl_alert_test 2.000s 70.623us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
lc_ctrl_tl_errors 3.000s 194.167us 1 1 100.00
tl_d_illegal_access 1 1 100.00
lc_ctrl_tl_errors 3.000s 194.167us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
lc_ctrl_csr_hw_reset 2.000s 98.983us 1 1 100.00
lc_ctrl_csr_rw 2.000s 69.447us 1 1 100.00
lc_ctrl_csr_aliasing 2.000s 23.987us 1 1 100.00
lc_ctrl_same_csr_outstanding 2.000s 121.814us 1 1 100.00
tl_d_partial_access 4 4 100.00
lc_ctrl_csr_hw_reset 2.000s 98.983us 1 1 100.00
lc_ctrl_csr_rw 2.000s 69.447us 1 1 100.00
lc_ctrl_csr_aliasing 2.000s 23.987us 1 1 100.00
lc_ctrl_same_csr_outstanding 2.000s 121.814us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
lc_ctrl_sec_cm 3.000s 1008.096us 1 1 100.00
lc_ctrl_tl_intg_err 3.000s 86.116us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
lc_ctrl_tl_intg_err 3.000s 86.116us 1 1 100.00
sec_cm_transition_config_regwen 1 1 100.00
lc_ctrl_regwen_during_op 6.000s 379.253us 1 1 100.00
sec_cm_manuf_state_sparse 1 2 50.00
lc_ctrl_state_failure 3601.000s 0.000us 0 1 0.00
lc_ctrl_sec_cm 3.000s 1008.096us 1 1 100.00
sec_cm_transition_ctr_sparse 1 2 50.00
lc_ctrl_state_failure 3601.000s 0.000us 0 1 0.00
lc_ctrl_sec_cm 3.000s 1008.096us 1 1 100.00
sec_cm_manuf_state_bkgn_chk 1 2 50.00
lc_ctrl_state_failure 3601.000s 0.000us 0 1 0.00
lc_ctrl_sec_cm 3.000s 1008.096us 1 1 100.00
sec_cm_transition_ctr_bkgn_chk 1 2 50.00
lc_ctrl_state_failure 3601.000s 0.000us 0 1 0.00
lc_ctrl_sec_cm 3.000s 1008.096us 1 1 100.00
sec_cm_state_config_sparse 1 2 50.00
lc_ctrl_state_failure 3601.000s 0.000us 0 1 0.00
lc_ctrl_sec_cm 3.000s 1008.096us 1 1 100.00
sec_cm_main_fsm_sparse 1 2 50.00
lc_ctrl_state_failure 3601.000s 0.000us 0 1 0.00
lc_ctrl_sec_cm 3.000s 1008.096us 1 1 100.00
sec_cm_kmac_fsm_sparse 1 2 50.00
lc_ctrl_state_failure 3601.000s 0.000us 0 1 0.00
lc_ctrl_sec_cm 3.000s 1008.096us 1 1 100.00
sec_cm_main_fsm_local_esc 1 2 50.00
lc_ctrl_state_failure 3601.000s 0.000us 0 1 0.00
lc_ctrl_sec_cm 3.000s 1008.096us 1 1 100.00
sec_cm_main_fsm_global_esc 1 1 100.00
lc_ctrl_security_escalation 6.000s 1103.036us 1 1 100.00
sec_cm_main_ctrl_flow_consistency 0 2 0.00
lc_ctrl_state_post_trans 3600.000s 0.000us 0 1 0.00
lc_ctrl_jtag_state_post_trans 3600.000s 0.000us 0 1 0.00
sec_cm_intersig_mubi 0 1 0.00
lc_ctrl_sec_mubi 3600.000s 0.000us 0 1 0.00
sec_cm_token_valid_ctrl_mubi 0 1 0.00
lc_ctrl_sec_mubi 3600.000s 0.000us 0 1 0.00
sec_cm_token_digest 1 1 100.00
lc_ctrl_sec_token_digest 6.000s 500.906us 1 1 100.00
sec_cm_token_mux_ctrl_redun 1 1 100.00
lc_ctrl_sec_token_mux 5.000s 959.004us 1 1 100.00
sec_cm_token_valid_mux_redun 1 1 100.00
lc_ctrl_sec_token_mux 5.000s 959.004us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 0 1 0.00
lc_ctrl_stress_all_with_rand_reset 3600.000s 0.000us 0 1 0.00

Error Messages

   Test seed line log context
Job timed out after * minutes 11 test runs
lc_ctrl_state_failure 106975711370362578204807530975232801700470975503386719301185804729380452437557 None
lc_ctrl_state_post_trans 55199784910418266464688984735630168744842429363580654150553162929053926940682 None
lc_ctrl_prog_failure 65794321876135565018056802622840912332193510084325654974012688115689404162126 None
lc_ctrl_errors 70625754801535995460652716313067217339888972302080602200477875045072161829014 None
lc_ctrl_jtag_state_failure 1235842482471114777355017212646266498417790184349612499977824940467353773749 None
lc_ctrl_jtag_state_post_trans 27772550173293357055219739560251808785583720214348602872335704720936237314748 None
lc_ctrl_jtag_prog_failure 45410778347612825770457184739417065293183539961016329752115936154945712124455 None
lc_ctrl_jtag_errors 8943318427213203574858345249589772495570803258206793246920374923236793215813 None
lc_ctrl_sec_mubi 59930837285708420999284095607203559489771986121676701581018397805069373349039 None
lc_ctrl_stress_all 103974121994155222920364056138091988691278268686141439077920413387982045567240 None
lc_ctrl_stress_all_with_rand_reset 34206903859806333234170780368275493911929066889581485244275990113320286684946 None