Simulation Results: lc_ctrl/volatile_unlock_enabled

 
31/08/2026 21:27:41 DVSim: v1.52.0 sha: 93d21e7 json Branch: master Tool: xcelium [24.03-s007]
Coverage statistics
  • Total
  • 88.25 %
  • code
  • 90.17 %
  • assert
  • 96.54 %
  • func
  • 78.06 %
  • block
  • 96.30 %
  • line
  • 96.31 %
  • branch
  • 90.62 %
  • toggle
  • 83.25 %
  • FSM
  • 90.48 %
Validation stages
V1
100.00%
V2
70.00%
V2S
60.00%
V3
0.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
lc_ctrl_smoke 2.000s 77.648us 1 1 100.00
csr_hw_reset 1 1 100.00
lc_ctrl_csr_hw_reset 1.000s 130.726us 1 1 100.00
csr_rw 1 1 100.00
lc_ctrl_csr_rw 1.000s 15.658us 1 1 100.00
csr_bit_bash 1 1 100.00
lc_ctrl_csr_bit_bash 2.000s 60.157us 1 1 100.00
csr_aliasing 1 1 100.00
lc_ctrl_csr_aliasing 1.000s 186.260us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
lc_ctrl_csr_mem_rw_with_rand_reset 1.000s 53.716us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
lc_ctrl_csr_rw 1.000s 15.658us 1 1 100.00
lc_ctrl_csr_aliasing 1.000s 186.260us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
state_post_trans 0 1 0.00
lc_ctrl_state_post_trans 3600.000s 0.000us 0 1 0.00
regwen_during_op 1 1 100.00
lc_ctrl_regwen_during_op 9.000s 3255.979us 1 1 100.00
rand_wr_claim_transition_if 1 1 100.00
lc_ctrl_claim_transition_if 2.000s 65.636us 1 1 100.00
lc_prog_failure 0 1 0.00
lc_ctrl_prog_failure 3600.000s 0.000us 0 1 0.00
lc_state_failure 0 1 0.00
lc_ctrl_state_failure 3600.000s 0.000us 0 1 0.00
lc_errors 0 1 0.00
lc_ctrl_errors 3600.000s 0.000us 0 1 0.00
security_escalation 1 7 14.29
lc_ctrl_state_failure 3600.000s 0.000us 0 1 0.00
lc_ctrl_prog_failure 3600.000s 0.000us 0 1 0.00
lc_ctrl_errors 3600.000s 0.000us 0 1 0.00
lc_ctrl_security_escalation 6.000s 364.370us 1 1 100.00
lc_ctrl_jtag_state_failure 3600.000s 0.000us 0 1 0.00
lc_ctrl_jtag_prog_failure 3600.000s 0.000us 0 1 0.00
lc_ctrl_jtag_errors 3601.000s 0.000us 0 1 0.00
jtag_access 10 13 76.92
lc_ctrl_jtag_smoke 3.000s 645.117us 1 1 100.00
lc_ctrl_jtag_state_post_trans 3600.000s 0.000us 0 1 0.00
lc_ctrl_jtag_prog_failure 3600.000s 0.000us 0 1 0.00
lc_ctrl_jtag_errors 3601.000s 0.000us 0 1 0.00
lc_ctrl_jtag_access 5.000s 251.492us 1 1 100.00
lc_ctrl_jtag_regwen_during_op 8.000s 697.877us 1 1 100.00
lc_ctrl_jtag_csr_hw_reset 3.000s 220.637us 1 1 100.00
lc_ctrl_jtag_csr_rw 3.000s 84.359us 1 1 100.00
lc_ctrl_jtag_csr_bit_bash 11.000s 1652.889us 1 1 100.00
lc_ctrl_jtag_csr_aliasing 3.000s 217.630us 1 1 100.00
lc_ctrl_jtag_same_csr_outstanding 2.000s 31.000us 1 1 100.00
lc_ctrl_jtag_csr_mem_rw_with_rand_reset 2.000s 514.669us 1 1 100.00
lc_ctrl_jtag_alert_test 2.000s 376.093us 1 1 100.00
jtag_priority 1 1 100.00
lc_ctrl_jtag_priority 10.000s 4472.252us 1 1 100.00
lc_ctrl_volatile_unlock 1 1 100.00
lc_ctrl_volatile_unlock_smoke 2.000s 44.843us 1 1 100.00
stress_all 0 1 0.00
lc_ctrl_stress_all 10802.081s 0.000us 0 1 0.00
alert_test 1 1 100.00
lc_ctrl_alert_test 2.000s 21.888us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
lc_ctrl_tl_errors 2.000s 113.391us 1 1 100.00
tl_d_illegal_access 1 1 100.00
lc_ctrl_tl_errors 2.000s 113.391us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
lc_ctrl_csr_hw_reset 1.000s 130.726us 1 1 100.00
lc_ctrl_csr_rw 1.000s 15.658us 1 1 100.00
lc_ctrl_csr_aliasing 1.000s 186.260us 1 1 100.00
lc_ctrl_same_csr_outstanding 3.000s 189.264us 1 1 100.00
tl_d_partial_access 4 4 100.00
lc_ctrl_csr_hw_reset 1.000s 130.726us 1 1 100.00
lc_ctrl_csr_rw 1.000s 15.658us 1 1 100.00
lc_ctrl_csr_aliasing 1.000s 186.260us 1 1 100.00
lc_ctrl_same_csr_outstanding 3.000s 189.264us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
lc_ctrl_sec_cm 4.000s 1526.843us 1 1 100.00
lc_ctrl_tl_intg_err 3.000s 463.450us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
lc_ctrl_tl_intg_err 3.000s 463.450us 1 1 100.00
sec_cm_transition_config_regwen 1 1 100.00
lc_ctrl_regwen_during_op 9.000s 3255.979us 1 1 100.00
sec_cm_manuf_state_sparse 1 2 50.00
lc_ctrl_state_failure 3600.000s 0.000us 0 1 0.00
lc_ctrl_sec_cm 4.000s 1526.843us 1 1 100.00
sec_cm_transition_ctr_sparse 1 2 50.00
lc_ctrl_state_failure 3600.000s 0.000us 0 1 0.00
lc_ctrl_sec_cm 4.000s 1526.843us 1 1 100.00
sec_cm_manuf_state_bkgn_chk 1 2 50.00
lc_ctrl_state_failure 3600.000s 0.000us 0 1 0.00
lc_ctrl_sec_cm 4.000s 1526.843us 1 1 100.00
sec_cm_transition_ctr_bkgn_chk 1 2 50.00
lc_ctrl_state_failure 3600.000s 0.000us 0 1 0.00
lc_ctrl_sec_cm 4.000s 1526.843us 1 1 100.00
sec_cm_state_config_sparse 1 2 50.00
lc_ctrl_state_failure 3600.000s 0.000us 0 1 0.00
lc_ctrl_sec_cm 4.000s 1526.843us 1 1 100.00
sec_cm_main_fsm_sparse 1 2 50.00
lc_ctrl_state_failure 3600.000s 0.000us 0 1 0.00
lc_ctrl_sec_cm 4.000s 1526.843us 1 1 100.00
sec_cm_kmac_fsm_sparse 1 2 50.00
lc_ctrl_state_failure 3600.000s 0.000us 0 1 0.00
lc_ctrl_sec_cm 4.000s 1526.843us 1 1 100.00
sec_cm_main_fsm_local_esc 1 2 50.00
lc_ctrl_state_failure 3600.000s 0.000us 0 1 0.00
lc_ctrl_sec_cm 4.000s 1526.843us 1 1 100.00
sec_cm_main_fsm_global_esc 1 1 100.00
lc_ctrl_security_escalation 6.000s 364.370us 1 1 100.00
sec_cm_main_ctrl_flow_consistency 0 2 0.00
lc_ctrl_state_post_trans 3600.000s 0.000us 0 1 0.00
lc_ctrl_jtag_state_post_trans 3600.000s 0.000us 0 1 0.00
sec_cm_intersig_mubi 0 1 0.00
lc_ctrl_sec_mubi 3600.000s 0.000us 0 1 0.00
sec_cm_token_valid_ctrl_mubi 0 1 0.00
lc_ctrl_sec_mubi 3600.000s 0.000us 0 1 0.00
sec_cm_token_digest 1 1 100.00
lc_ctrl_sec_token_digest 5.000s 1237.148us 1 1 100.00
sec_cm_token_mux_ctrl_redun 1 1 100.00
lc_ctrl_sec_token_mux 5.000s 849.399us 1 1 100.00
sec_cm_token_valid_mux_redun 1 1 100.00
lc_ctrl_sec_token_mux 5.000s 849.399us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 0 1 0.00
lc_ctrl_stress_all_with_rand_reset 3.000s 211.280us 0 1 0.00

Error Messages

   Test seed line log context
Job timed out after * minutes 10 test runs
lc_ctrl_state_failure 18642758521390254314169290010893002691461457058879211184681415295276852591938 None
lc_ctrl_state_post_trans 9050442462050478423688425080653512899808805093692429429002672562599332880650 None
lc_ctrl_prog_failure 76123535785172871313041992781688851974159435352757047944873005932174356849811 None
lc_ctrl_errors 96486453109746223583055684866021891347601722679663214298708523223488456094282 None
lc_ctrl_jtag_state_failure 9669755514074251773873974905583664088621139410081051280099738099331360925430 None
lc_ctrl_jtag_state_post_trans 81248348258622724509139986821749389857028564279246346376087297808235326902130 None
lc_ctrl_jtag_prog_failure 76271661684129556600685531236160564979502291824950474763111756791166412076509 None
lc_ctrl_jtag_errors 11387323954262108091790715480311430505839217894354391523203241678629414270428 None
lc_ctrl_sec_mubi 101613096470317345709413754694605071537204162425537148114539640731270331120012 None
lc_ctrl_stress_all 54818894486253923518950530571243212733025481178916107026878763621239548802609 None
UVM_ERROR (cip_base_vseq.sv:1297) [lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. 1 test run
lc_ctrl_stress_all_with_rand_reset 22863827062667404512718378870010499301728627247472763077576929153285599280986 182
UVM_INFO @ 211280260 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---