Simulation Results: mbx

 
31/08/2026 21:27:41 DVSim: v1.52.0 sha: 93d21e7 json Branch: master Tool: xcelium [24.03-s007]
Coverage statistics
  • Total
  • 86.19 %
  • code
  • 87.28 %
  • assert
  • 96.96 %
  • func
  • 74.32 %
  • block
  • 95.10 %
  • line
  • 95.54 %
  • branch
  • 86.85 %
  • toggle
  • 79.45 %
Validation stages
V1
83.33%
V2
63.64%
V2S
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
mbx_smoke 1 1 100.00
mbx_smoke 85.000s 84046.276us 1 1 100.00
csr_hw_reset 1 1 100.00
mbx_csr_hw_reset 2.000s 44.492us 1 1 100.00
csr_rw 1 1 100.00
mbx_csr_rw 1.000s 65.360us 1 1 100.00
csr_bit_bash 1 1 100.00
mbx_csr_bit_bash 4.000s 240.414us 1 1 100.00
csr_aliasing 1 1 100.00
mbx_csr_aliasing 1.000s 14.348us 1 1 100.00
csr_mem_rw_with_rand_reset 0 1 0.00
mbx_csr_mem_rw_with_rand_reset 2.000s 19.857us 0 1 0.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
mbx_csr_rw 1.000s 65.360us 1 1 100.00
mbx_csr_aliasing 1.000s 14.348us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
mbx_stress 0 1 0.00
mbx_stress 10.000s 843.561us 0 1 0.00
mbx_max_activity 0 1 0.00
mbx_stress_zero_delays 9.000s 318.604us 0 1 0.00
mbx_imbx_oob 0 1 0.00
mbx_imbx_oob 6.000s 1136.573us 0 1 0.00
mbx_doe_intr_msg 1 1 100.00
mbx_doe_intr_msg 11.000s 2340.720us 1 1 100.00
alert_test 1 1 100.00
mbx_alert_test 2.000s 15.440us 1 1 100.00
intr_test 1 1 100.00
mbx_intr_test 1.000s 102.298us 1 1 100.00
tl_d_oob_addr_access 0 1 0.00
mbx_tl_errors 1.000s 6.244us 0 1 0.00
tl_d_illegal_access 0 1 0.00
mbx_tl_errors 1.000s 6.244us 0 1 0.00
tl_d_outstanding_access 4 4 100.00
mbx_csr_hw_reset 2.000s 44.492us 1 1 100.00
mbx_csr_rw 1.000s 65.360us 1 1 100.00
mbx_csr_aliasing 1.000s 14.348us 1 1 100.00
mbx_same_csr_outstanding 1.000s 19.434us 1 1 100.00
tl_d_partial_access 4 4 100.00
mbx_csr_hw_reset 2.000s 44.492us 1 1 100.00
mbx_csr_rw 1.000s 65.360us 1 1 100.00
mbx_csr_aliasing 1.000s 14.348us 1 1 100.00
mbx_same_csr_outstanding 1.000s 19.434us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
mbx_tl_intg_err 2.000s 321.891us 1 1 100.00
mbx_sec_cm 2.000s 12.016us 1 1 100.00

Error Messages

   Test seed line log context
UVM_ERROR (mbx_scoreboard.sv:500) [scoreboard] Check failed item.d_data == exp_data (* [*] vs * [*]) RDATA read data mismatched 2 test runs
mbx_stress 6091970951627412229771097863896323939994774059225314990901841328863793588868 786
UVM_INFO @ 843561097 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
mbx_stress_zero_delays 96483421130122168403756070534201283897768393987919550340751248349609442037443 412
UVM_INFO @ 318604347 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (cip_base_scoreboard.sv:696) scoreboard [scoreboard] On interface mbx_soc_reg_block, item had unexpected d_error value(predicted *, but saw *). 2 test runs
mbx_tl_errors 2590502335434380721268340610473910252909304431995415691296342985840200943446 85
TL item was: req: (cip_tl_seq_item@18478) { a_addr: 'h363661d0 a_data: 'ha2c357e8 a_mask: 'h3 a_size: 'h2 a_param: 'h0 a_source: 'ha9 a_opcode: 'h1 a_user: 'h27c5d d_param: 'h0 d_source: 'ha9 d_data: 'h0 d_size: 'h2 d_opcode: 'h0 d_error: 'h0 d_sink: 'h0 d_user: 'h1caa a_valid_delay: 'h0 d_valid_delay: 'h0 a_valid_len: 'h0 d_valid_len: 'h0 req_abort_after_a_valid_len: 'h0 rsp_abort_after_d_valid_len: 'h0 req_completed: 'h0 rsp_completed: 'h0 tl_intg_err_type: TlIntgErrNone max_ecc_errors: 'h3 }
Reasons for predicted error: '{"Unsupported partial write"}.
UVM_INFO @ 6243583 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
mbx_csr_mem_rw_with_rand_reset 55981991391967177176793200375689972118950204597967769354071596713957599440690 92
TL item was: req: (cip_tl_seq_item@23839) { a_addr: 'haa5ff690 a_data: 'h87332f2d a_mask: 'h3 a_size: 'h1 a_param: 'h0 a_source: 'hd4 a_opcode: 'h1 a_user: 'h248ea d_param: 'h0 d_source: 'hd4 d_data: 'h0 d_size: 'h1 d_opcode: 'h0 d_error: 'h0 d_sink: 'h0 d_user: 'h10aa a_valid_delay: 'h0 d_valid_delay: 'h0 a_valid_len: 'h0 d_valid_len: 'h0 req_abort_after_a_valid_len: 'h0 rsp_abort_after_d_valid_len: 'h0 req_completed: 'h0 rsp_completed: 'h0 tl_intg_err_type: TlIntgErrNone max_ecc_errors: 'h3 }
Reasons for predicted error: '{"Unsupported partial write"}.
UVM_INFO @ 19857005 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (mbx_scoreboard.sv:537) [scoreboard] Check failed m_ib_data_q.size() != * (* [*] vs * [*]) No write data in WDATA register 1 test run
mbx_imbx_oob 107516578854209187796007604349047692899723277864474530474285940296184231005898 109
UVM_INFO @ 1136573394 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---