Simulation Results: otbn

 
31/08/2026 21:27:41 DVSim: v1.52.0 sha: 93d21e7 json Branch: master Tool: xcelium [24.03-s007]
Coverage statistics
  • Total
  • 89.73 %
  • code
  • 81.85 %
  • assert
  • 89.45 %
  • func
  • 97.88 %
  • block
  • 97.74 %
  • line
  • 97.95 %
  • branch
  • 81.87 %
  • toggle
  • 81.39 %
  • FSM
  • 66.20 %
Validation stages
V1
100.00%
V2
92.86%
V2S
96.00%
V3
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 2 2 100.00
otbn_smoke 13.000s 272.400us 1 1 100.00
otbn_smoke_vectorized 9.000s 64.595us 1 1 100.00
single_binary 1 1 100.00
otbn_single 22.000s 51.006us 1 1 100.00
csr_hw_reset 1 1 100.00
otbn_csr_hw_reset 5.000s 27.566us 1 1 100.00
csr_rw 1 1 100.00
otbn_csr_rw 5.000s 12.929us 1 1 100.00
csr_bit_bash 1 1 100.00
otbn_csr_bit_bash 9.000s 320.436us 1 1 100.00
csr_aliasing 1 1 100.00
otbn_csr_aliasing 5.000s 11.806us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
otbn_csr_mem_rw_with_rand_reset 8.000s 25.743us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
otbn_csr_rw 5.000s 12.929us 1 1 100.00
otbn_csr_aliasing 5.000s 11.806us 1 1 100.00
mem_walk 1 1 100.00
otbn_mem_walk 50.000s 3242.803us 1 1 100.00
mem_partial_access 1 1 100.00
otbn_mem_partial_access 32.000s 1005.128us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
reset_recovery 1 1 100.00
otbn_reset 33.000s 131.185us 1 1 100.00
multi_error 0 1 0.00
otbn_multi_err 19.000s 39.875us 0 1 0.00
back_to_back 1 1 100.00
otbn_multi 49.000s 76.319us 1 1 100.00
stress_all 1 1 100.00
otbn_stress_all 107.000s 2551.427us 1 1 100.00
lc_escalation 1 1 100.00
otbn_escalate 9.000s 69.540us 1 1 100.00
zero_state_err_urnd 1 1 100.00
otbn_zero_state_err_urnd 7.000s 58.392us 1 1 100.00
sw_errs_fatal_chk 1 1 100.00
otbn_sw_errs_fatal_chk 10.000s 54.640us 1 1 100.00
alert_test 1 1 100.00
otbn_alert_test 6.000s 17.642us 1 1 100.00
intr_test 1 1 100.00
otbn_intr_test 5.000s 64.364us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
otbn_tl_errors 7.000s 38.785us 1 1 100.00
tl_d_illegal_access 1 1 100.00
otbn_tl_errors 7.000s 38.785us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
otbn_csr_hw_reset 5.000s 27.566us 1 1 100.00
otbn_csr_rw 5.000s 12.929us 1 1 100.00
otbn_csr_aliasing 5.000s 11.806us 1 1 100.00
otbn_same_csr_outstanding 6.000s 65.307us 1 1 100.00
tl_d_partial_access 4 4 100.00
otbn_csr_hw_reset 5.000s 27.566us 1 1 100.00
otbn_csr_rw 5.000s 12.929us 1 1 100.00
otbn_csr_aliasing 5.000s 11.806us 1 1 100.00
otbn_same_csr_outstanding 6.000s 65.307us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
mem_integrity 2 2 100.00
otbn_imem_err 11.000s 16.518us 1 1 100.00
otbn_dmem_err 13.000s 86.328us 1 1 100.00
internal_integrity 4 4 100.00
otbn_alu_bignum_mod_err 15.000s 59.337us 1 1 100.00
otbn_controller_ispr_rdata_err 12.000s 120.055us 1 1 100.00
otbn_mac_bignum_acc_err 9.000s 56.268us 1 1 100.00
otbn_urnd_err 10.000s 18.679us 1 1 100.00
illegal_bus_access 1 1 100.00
otbn_illegal_mem_acc 7.000s 31.254us 1 1 100.00
otbn_mem_gnt_acc_err 1 1 100.00
otbn_mem_gnt_acc_err 11.000s 23.750us 1 1 100.00
otbn_non_sec_partial_wipe 1 1 100.00
otbn_partial_wipe 9.000s 73.363us 1 1 100.00
tl_intg_err 2 2 100.00
otbn_sec_cm 577.000s 2141.810us 1 1 100.00
otbn_tl_intg_err 26.000s 277.459us 1 1 100.00
passthru_mem_tl_intg_err 0 1 0.00
otbn_passthru_mem_tl_intg_err 9.000s 110.317us 0 1 0.00
prim_fsm_check 1 1 100.00
otbn_sec_cm 577.000s 2141.810us 1 1 100.00
prim_count_check 1 1 100.00
otbn_sec_cm 577.000s 2141.810us 1 1 100.00
sec_cm_mem_scramble 1 1 100.00
otbn_smoke 13.000s 272.400us 1 1 100.00
sec_cm_data_mem_integrity 1 1 100.00
otbn_dmem_err 13.000s 86.328us 1 1 100.00
sec_cm_instruction_mem_integrity 1 1 100.00
otbn_imem_err 11.000s 16.518us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
otbn_tl_intg_err 26.000s 277.459us 1 1 100.00
sec_cm_controller_fsm_global_esc 1 1 100.00
otbn_escalate 9.000s 69.540us 1 1 100.00
sec_cm_controller_fsm_local_esc 5 5 100.00
otbn_imem_err 11.000s 16.518us 1 1 100.00
otbn_dmem_err 13.000s 86.328us 1 1 100.00
otbn_zero_state_err_urnd 7.000s 58.392us 1 1 100.00
otbn_illegal_mem_acc 7.000s 31.254us 1 1 100.00
otbn_sec_cm 577.000s 2141.810us 1 1 100.00
sec_cm_controller_fsm_sparse 1 1 100.00
otbn_sec_cm 577.000s 2141.810us 1 1 100.00
sec_cm_scramble_key_sideload 1 1 100.00
otbn_single 22.000s 51.006us 1 1 100.00
sec_cm_scramble_ctrl_fsm_local_esc 5 5 100.00
otbn_imem_err 11.000s 16.518us 1 1 100.00
otbn_dmem_err 13.000s 86.328us 1 1 100.00
otbn_zero_state_err_urnd 7.000s 58.392us 1 1 100.00
otbn_illegal_mem_acc 7.000s 31.254us 1 1 100.00
otbn_sec_cm 577.000s 2141.810us 1 1 100.00
sec_cm_scramble_ctrl_fsm_sparse 1 1 100.00
otbn_sec_cm 577.000s 2141.810us 1 1 100.00
sec_cm_start_stop_ctrl_fsm_global_esc 1 1 100.00
otbn_escalate 9.000s 69.540us 1 1 100.00
sec_cm_start_stop_ctrl_fsm_local_esc 5 5 100.00
otbn_imem_err 11.000s 16.518us 1 1 100.00
otbn_dmem_err 13.000s 86.328us 1 1 100.00
otbn_zero_state_err_urnd 7.000s 58.392us 1 1 100.00
otbn_illegal_mem_acc 7.000s 31.254us 1 1 100.00
otbn_sec_cm 577.000s 2141.810us 1 1 100.00
sec_cm_start_stop_ctrl_fsm_sparse 1 1 100.00
otbn_sec_cm 577.000s 2141.810us 1 1 100.00
sec_cm_data_reg_sw_sca 1 1 100.00
otbn_single 22.000s 51.006us 1 1 100.00
sec_cm_ctrl_redun 1 1 100.00
otbn_ctrl_redun 11.000s 107.327us 1 1 100.00
sec_cm_pc_ctrl_flow_redun 1 1 100.00
otbn_pc_ctrl_flow_redun 10.000s 13.445us 1 1 100.00
sec_cm_rnd_bus_consistency 1 1 100.00
otbn_rnd_sec_cm 41.000s 462.339us 1 1 100.00
sec_cm_rnd_rng_digest 1 1 100.00
otbn_rnd_sec_cm 41.000s 462.339us 1 1 100.00
sec_cm_rf_base_data_reg_sw_integrity 1 1 100.00
otbn_rf_base_intg_err 11.000s 55.714us 1 1 100.00
sec_cm_rf_base_data_reg_sw_glitch_detect 1 1 100.00
otbn_sec_cm 577.000s 2141.810us 1 1 100.00
sec_cm_stack_wr_ptr_ctr_redun 1 1 100.00
otbn_sec_cm 577.000s 2141.810us 1 1 100.00
sec_cm_rf_bignum_data_reg_sw_integrity 1 1 100.00
otbn_rf_bignum_intg_err 12.000s 220.473us 1 1 100.00
sec_cm_rf_bignum_data_reg_sw_glitch_detect 1 1 100.00
otbn_sec_cm 577.000s 2141.810us 1 1 100.00
sec_cm_loop_stack_ctr_redun 1 1 100.00
otbn_sec_cm 577.000s 2141.810us 1 1 100.00
sec_cm_loop_stack_addr_integrity 1 1 100.00
otbn_stack_addr_integ_chk 14.000s 31.026us 1 1 100.00
sec_cm_call_stack_addr_integrity 1 1 100.00
otbn_stack_addr_integ_chk 14.000s 31.026us 1 1 100.00
sec_cm_start_stop_ctrl_state_consistency 1 1 100.00
otbn_sec_wipe_err 13.000s 115.315us 1 1 100.00
sec_cm_data_mem_sec_wipe 1 1 100.00
otbn_single 22.000s 51.006us 1 1 100.00
sec_cm_instruction_mem_sec_wipe 1 1 100.00
otbn_single 22.000s 51.006us 1 1 100.00
sec_cm_data_reg_sw_sec_wipe 1 1 100.00
otbn_single 22.000s 51.006us 1 1 100.00
sec_cm_write_mem_integrity 1 1 100.00
otbn_multi 49.000s 76.319us 1 1 100.00
sec_cm_ctrl_flow_count 1 1 100.00
otbn_single 22.000s 51.006us 1 1 100.00
sec_cm_ctrl_flow_sca 1 1 100.00
otbn_single 22.000s 51.006us 1 1 100.00
sec_cm_data_mem_sw_noaccess 1 1 100.00
otbn_sw_no_acc 8.000s 42.401us 1 1 100.00
sec_cm_key_sideload 1 1 100.00
otbn_single 22.000s 51.006us 1 1 100.00
sec_cm_tlul_fifo_ctr_redun 1 1 100.00
otbn_sec_cm 577.000s 2141.810us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 1 1 100.00
otbn_stress_all_with_rand_reset 392.000s 1647.517us 1 1 100.00

Error Messages

   Test seed line log context
UVM_FATAL (otbn_scoreboard.sv:551) scoreboard [scoreboard] We saw a STATUS change * cycles ago that implied we'd get a recov alert but it still hasn't arrived. 2 test runs
otbn_multi_err 52008163042649550684364041218851591833410623524662790384199176533643121960614 231
UVM_INFO @ 39874559 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otbn_passthru_mem_tl_intg_err 113276040334811388470026553710757680238556719751580869649477071288160362474744 91
UVM_INFO @ 110317470 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---