Simulation Results: rom_ctrl/64kb

 
31/08/2026 21:27:41 DVSim: v1.52.0 sha: 93d21e7 json Branch: master Tool: xcelium [24.03-s007]
Coverage statistics
  • Total
  • 88.59 %
  • code
  • 79.31 %
  • assert
  • 97.38 %
  • func
  • 89.07 %
  • block
  • 77.99 %
  • line
  • 78.48 %
  • branch
  • 77.91 %
  • toggle
  • 84.65 %
  • FSM
  • 76.19 %
Validation stages
V1
100.00%
V2
88.89%
V2S
83.33%
V3
0.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
rom_ctrl_smoke 6.000s 734.170us 1 1 100.00
csr_hw_reset 1 1 100.00
rom_ctrl_csr_hw_reset 5.000s 54.110us 1 1 100.00
csr_rw 1 1 100.00
rom_ctrl_csr_rw 4.000s 53.859us 1 1 100.00
csr_bit_bash 1 1 100.00
rom_ctrl_csr_bit_bash 4.000s 112.990us 1 1 100.00
csr_aliasing 1 1 100.00
rom_ctrl_csr_aliasing 3.000s 104.962us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
rom_ctrl_csr_mem_rw_with_rand_reset 5.000s 64.165us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
rom_ctrl_csr_rw 4.000s 53.859us 1 1 100.00
rom_ctrl_csr_aliasing 3.000s 104.962us 1 1 100.00
mem_walk 1 1 100.00
rom_ctrl_mem_walk 2.000s 60.168us 1 1 100.00
mem_partial_access 1 1 100.00
rom_ctrl_mem_partial_access 3.000s 126.892us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
max_throughput_chk 0 1 0.00
rom_ctrl_max_throughput_chk 4.000s 31.523us 0 1 0.00
stress_all 1 1 100.00
rom_ctrl_stress_all 12.000s 730.290us 1 1 100.00
kmac_err_chk 1 1 100.00
rom_ctrl_kmac_err_chk 5.000s 74.896us 1 1 100.00
alert_test 1 1 100.00
rom_ctrl_alert_test 3.000s 54.311us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
rom_ctrl_tl_errors 5.000s 130.705us 1 1 100.00
tl_d_illegal_access 1 1 100.00
rom_ctrl_tl_errors 5.000s 130.705us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
rom_ctrl_csr_hw_reset 5.000s 54.110us 1 1 100.00
rom_ctrl_csr_rw 4.000s 53.859us 1 1 100.00
rom_ctrl_csr_aliasing 3.000s 104.962us 1 1 100.00
rom_ctrl_same_csr_outstanding 5.000s 59.284us 1 1 100.00
tl_d_partial_access 4 4 100.00
rom_ctrl_csr_hw_reset 5.000s 54.110us 1 1 100.00
rom_ctrl_csr_rw 4.000s 53.859us 1 1 100.00
rom_ctrl_csr_aliasing 3.000s 104.962us 1 1 100.00
rom_ctrl_same_csr_outstanding 5.000s 59.284us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
corrupt_sig_fatal_chk 0 1 0.00
rom_ctrl_corrupt_sig_fatal_chk 3601.000s 0.000us 0 1 0.00
passthru_mem_tl_intg_err 1 1 100.00
rom_ctrl_passthru_mem_tl_intg_err 12.000s 1462.318us 1 1 100.00
tl_intg_err 2 2 100.00
rom_ctrl_sec_cm 121.000s 1078.173us 1 1 100.00
rom_ctrl_tl_intg_err 50.000s 726.837us 1 1 100.00
prim_fsm_check 1 1 100.00
rom_ctrl_sec_cm 121.000s 1078.173us 1 1 100.00
prim_count_check 1 1 100.00
rom_ctrl_sec_cm 121.000s 1078.173us 1 1 100.00
sec_cm_checker_ctr_consistency 0 1 0.00
rom_ctrl_corrupt_sig_fatal_chk 3601.000s 0.000us 0 1 0.00
sec_cm_checker_ctrl_flow_consistency 0 1 0.00
rom_ctrl_corrupt_sig_fatal_chk 3601.000s 0.000us 0 1 0.00
sec_cm_checker_fsm_local_esc 0 1 0.00
rom_ctrl_corrupt_sig_fatal_chk 3601.000s 0.000us 0 1 0.00
sec_cm_compare_ctrl_flow_consistency 0 1 0.00
rom_ctrl_corrupt_sig_fatal_chk 3601.000s 0.000us 0 1 0.00
sec_cm_compare_ctr_consistency 0 1 0.00
rom_ctrl_corrupt_sig_fatal_chk 3601.000s 0.000us 0 1 0.00
sec_cm_compare_ctr_redun 1 1 100.00
rom_ctrl_sec_cm 121.000s 1078.173us 1 1 100.00
sec_cm_fsm_sparse 1 1 100.00
rom_ctrl_sec_cm 121.000s 1078.173us 1 1 100.00
sec_cm_mem_scramble 1 1 100.00
rom_ctrl_smoke 6.000s 734.170us 1 1 100.00
sec_cm_mem_digest 1 1 100.00
rom_ctrl_smoke 6.000s 734.170us 1 1 100.00
sec_cm_intersig_mubi 1 1 100.00
rom_ctrl_smoke 6.000s 734.170us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
rom_ctrl_tl_intg_err 50.000s 726.837us 1 1 100.00
sec_cm_bus_local_esc 1 2 50.00
rom_ctrl_corrupt_sig_fatal_chk 3601.000s 0.000us 0 1 0.00
rom_ctrl_kmac_err_chk 5.000s 74.896us 1 1 100.00
sec_cm_mux_mubi 0 1 0.00
rom_ctrl_corrupt_sig_fatal_chk 3601.000s 0.000us 0 1 0.00
sec_cm_mux_consistency 0 1 0.00
rom_ctrl_corrupt_sig_fatal_chk 3601.000s 0.000us 0 1 0.00
sec_cm_ctrl_redun 0 1 0.00
rom_ctrl_corrupt_sig_fatal_chk 3601.000s 0.000us 0 1 0.00
sec_cm_ctrl_mem_integrity 1 1 100.00
rom_ctrl_passthru_mem_tl_intg_err 12.000s 1462.318us 1 1 100.00
sec_cm_tlul_fifo_ctr_redun 1 1 100.00
rom_ctrl_sec_cm 121.000s 1078.173us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 0 1 0.00
rom_ctrl_stress_all_with_rand_reset 3600.000s 0.000us 0 1 0.00

Error Messages

   Test seed line log context
Job timed out after * minutes 2 test runs
rom_ctrl_corrupt_sig_fatal_chk 94177030437267065035136177811269658852546071484198236468049511205709853010342 None
rom_ctrl_stress_all_with_rand_reset 99061937004747972419984133638153223691225055687156604210280590399513179304101 None
UVM_ERROR (rom_ctrl_throughput_vseq.sv:52) [rom_ctrl_throughput_vseq] Check failed num_cycles == num_mem_reads + * (* [*] vs * [*]) 1 test run
rom_ctrl_max_throughput_chk 69213999010936427244346900791333048726696543808145797569698873221293630699685 88
UVM_INFO @ 31523324 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---