Simulation Results: rv_dm/use_dmi_interface

 
31/08/2026 21:27:41 DVSim: v1.52.0 sha: 93d21e7 json Branch: master Tool: xcelium [24.03-s007]
Coverage statistics
  • Total
  • 91.25 %
  • code
  • 82.02 %
  • assert
  • 96.82 %
  • func
  • 94.90 %
  • block
  • 93.24 %
  • line
  • 93.82 %
  • branch
  • 81.65 %
  • toggle
  • 72.25 %
  • FSM
  • 80.36 %
Validation stages
V1
92.59%
V2
73.91%
V2S
100.00%
V3
100.00%
unmapped
0.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
rv_dm_smoke 41.000s 1851.989us 1 1 100.00
jtag_dtm_csr_hw_reset 1 1 100.00
rv_dm_jtag_dtm_csr_hw_reset 41.000s 149.260us 1 1 100.00
jtag_dtm_csr_rw 1 1 100.00
rv_dm_jtag_dtm_csr_rw 50.000s 364.140us 1 1 100.00
jtag_dtm_csr_bit_bash 1 1 100.00
rv_dm_jtag_dtm_csr_bit_bash 44.000s 4091.805us 1 1 100.00
jtag_dtm_csr_aliasing 1 1 100.00
rv_dm_jtag_dtm_csr_aliasing 53.000s 424.041us 1 1 100.00
jtag_dmi_csr_hw_reset 1 1 100.00
rv_dm_jtag_dmi_csr_hw_reset 44.000s 1990.629us 1 1 100.00
jtag_dmi_csr_rw 1 1 100.00
rv_dm_jtag_dmi_csr_rw 47.000s 5583.692us 1 1 100.00
jtag_dmi_csr_bit_bash 1 1 100.00
rv_dm_jtag_dmi_csr_bit_bash 52.000s 25523.346us 1 1 100.00
jtag_dmi_csr_aliasing 1 1 100.00
rv_dm_jtag_dmi_csr_aliasing 59.000s 7497.757us 1 1 100.00
jtag_dmi_cmderr_busy 1 1 100.00
rv_dm_cmderr_busy 41.000s 496.594us 1 1 100.00
jtag_dmi_cmderr_not_supported 1 1 100.00
rv_dm_cmderr_not_supported 52.000s 372.283us 1 1 100.00
cmderr_exception 1 1 100.00
rv_dm_cmderr_exception 48.000s 799.691us 1 1 100.00
mem_tl_access_resuming 0 1 0.00
rv_dm_mem_tl_access_resuming 43.000s 121.314us 0 1 0.00
mem_tl_access_halted 1 1 100.00
rv_dm_mem_tl_access_halted 51.000s 117.247us 1 1 100.00
cmderr_halt_resume 1 1 100.00
rv_dm_cmderr_halt_resume 42.000s 1519.078us 1 1 100.00
dataaddr_rw_access 1 1 100.00
rv_dm_dataaddr_rw_access 47.000s 107.031us 1 1 100.00
halt_resume 1 1 100.00
rv_dm_halt_resume_whereto 45.000s 271.518us 1 1 100.00
progbuf_busy 1 1 100.00
rv_dm_cmderr_busy 41.000s 496.594us 1 1 100.00
abstractcmd_status 1 1 100.00
rv_dm_abstractcmd_status 47.000s 140.784us 1 1 100.00
progbuf_read_write_execute 1 1 100.00
rv_dm_progbuf_read_write_execute 36.000s 296.810us 1 1 100.00
progbuf_exception 1 1 100.00
rv_dm_cmderr_exception 48.000s 799.691us 1 1 100.00
rom_read_access 0 1 0.00
rv_dm_rom_read_access 44.000s 153.064us 0 1 0.00
csr_hw_reset 1 1 100.00
rv_dm_csr_hw_reset 42.000s 357.897us 1 1 100.00
csr_rw 1 1 100.00
rv_dm_csr_rw 53.000s 46.045us 1 1 100.00
csr_bit_bash 1 1 100.00
rv_dm_csr_bit_bash 81.000s 4158.204us 1 1 100.00
csr_aliasing 1 1 100.00
rv_dm_csr_aliasing 66.000s 10003.527us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
rv_dm_csr_mem_rw_with_rand_reset 44.000s 167.851us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
rv_dm_csr_aliasing 66.000s 10003.527us 1 1 100.00
rv_dm_csr_rw 53.000s 46.045us 1 1 100.00
mem_walk 1 1 100.00
rv_dm_mem_walk 51.000s 33.490us 1 1 100.00
mem_partial_access 1 1 100.00
rv_dm_mem_partial_access 50.000s 96.248us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
idcode 1 1 100.00
rv_dm_smoke 41.000s 1851.989us 1 1 100.00
jtag_dtm_hard_reset 1 1 100.00
rv_dm_jtag_dtm_hard_reset 51.000s 249.412us 1 1 100.00
jtag_dtm_idle_hint 1 1 100.00
rv_dm_jtag_dtm_idle_hint 52.000s 225.160us 1 1 100.00
jtag_dmi_failed_op 1 1 100.00
rv_dm_dmi_failed_op 52.000s 349.013us 1 1 100.00
jtag_dmi_dm_inactive 1 1 100.00
rv_dm_jtag_dmi_dm_inactive 48.000s 779.683us 1 1 100.00
sba 0 2 0.00
rv_dm_sba_tl_access 53.000s 2033.856us 0 1 0.00
rv_dm_delayed_resp_sba_tl_access 47.000s 750.333us 0 1 0.00
bad_sba 1 1 100.00
rv_dm_bad_sba_tl_access 44.000s 1546.639us 1 1 100.00
sba_autoincrement 0 1 0.00
rv_dm_autoincr_sba_tl_access 66.000s 10766.733us 0 1 0.00
jtag_dmi_debug_disabled 0 1 0.00
rv_dm_jtag_dmi_debug_disabled 42.000s 622.783us 0 1 0.00
sba_debug_disabled 1 1 100.00
rv_dm_sba_debug_disabled 47.000s 882.329us 1 1 100.00
ndmreset_req 1 1 100.00
rv_dm_ndmreset_req 51.000s 228.684us 1 1 100.00
hart_unavail 0 1 0.00
rv_dm_hart_unavail 43.000s 54.764us 0 1 0.00
tap_ctrl_transitions 2 2 100.00
rv_dm_tap_fsm 65.000s 9181.771us 1 1 100.00
rv_dm_tap_fsm_rand_reset 88.000s 6450.370us 1 1 100.00
hartsel_warl 1 1 100.00
rv_dm_hartsel_warl 45.000s 68.005us 1 1 100.00
stress_all 0 1 0.00
rv_dm_stress_all 45.000s 2470.809us 0 1 0.00
alert_test 1 1 100.00
rv_dm_alert_test 36.000s 42.361us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
rv_dm_tl_errors 47.000s 150.659us 1 1 100.00
tl_d_illegal_access 1 1 100.00
rv_dm_tl_errors 47.000s 150.659us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
rv_dm_csr_aliasing 66.000s 10003.527us 1 1 100.00
rv_dm_csr_hw_reset 42.000s 357.897us 1 1 100.00
rv_dm_csr_rw 53.000s 46.045us 1 1 100.00
rv_dm_same_csr_outstanding 41.000s 621.139us 1 1 100.00
tl_d_partial_access 4 4 100.00
rv_dm_csr_aliasing 66.000s 10003.527us 1 1 100.00
rv_dm_csr_hw_reset 42.000s 357.897us 1 1 100.00
rv_dm_csr_rw 53.000s 46.045us 1 1 100.00
rv_dm_same_csr_outstanding 41.000s 621.139us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
rv_dm_sec_cm 49.000s 1382.953us 1 1 100.00
rv_dm_tl_intg_err 59.000s 2097.416us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
rv_dm_tl_intg_err 59.000s 2097.416us 1 1 100.00
sec_cm_lc_hw_debug_en_intersig_mubi 2 2 100.00
rv_dm_sba_debug_disabled 47.000s 882.329us 1 1 100.00
rv_dm_debug_disabled 43.000s 61.047us 1 1 100.00
sec_cm_lc_dft_en_intersig_mubi 2 2 100.00
rv_dm_sba_debug_disabled 47.000s 882.329us 1 1 100.00
rv_dm_debug_disabled 43.000s 61.047us 1 1 100.00
sec_cm_otp_dis_rv_dm_late_debug_intersig_mubi 1 1 100.00
rv_dm_smoke 41.000s 1851.989us 1 1 100.00
sec_cm_dm_en_ctrl_lc_gated 1 1 100.00
rv_dm_buffered_enable 48.000s 476.704us 1 1 100.00
sec_cm_sba_tl_lc_gate_fsm_sparse 1 1 100.00
rv_dm_sparse_lc_gate_fsm 44.000s 71.991us 1 1 100.00
sec_cm_mem_tl_lc_gate_fsm_sparse 1 1 100.00
rv_dm_sparse_lc_gate_fsm 44.000s 71.991us 1 1 100.00
sec_cm_exec_ctrl_mubi 1 1 100.00
rv_dm_buffered_enable 48.000s 476.704us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 1 1 100.00
rv_dm_stress_all_with_rand_reset 89.000s 3268.942us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
Unmapped 0 1 0.00
rv_dm_scanmode 210.000s 300000.000us 0 1 0.00

Error Messages

   Test seed line log context
UVM_ERROR (rv_dm_scoreboard.sv:481) [scoreboard] sba_tl_access_q item uncompared: 3 test runs
rv_dm_sba_tl_access 35963773641248839211898368033023773998812304264329873911585042044853177119384 87
-------------------------------------------------------------------
Name Type Size Value
-------------------------------------------------------------------
req cip_tl_seq_item - @23875
rv_dm_delayed_resp_sba_tl_access 15635364012834577469710148643123871640245818262409860670811521721203600765409 87
-------------------------------------------------------------------
Name Type Size Value
-------------------------------------------------------------------
req cip_tl_seq_item - @23816
rv_dm_autoincr_sba_tl_access 60663146282372177739764272686537879146113696337877544574857969558630778359347 147
-------------------------------------------------------------------
Name Type Size Value
-------------------------------------------------------------------
req cip_tl_seq_item - @24050
UVM_ERROR (rv_dm_mem_tl_access_resuming_vseq.sv:56) [rv_dm_mem_tl_access_resuming_vseq] Check failed jtag_dmi_ral.dmstatus.anyhalted.get_mirrored_value() == *'b* (* [*] vs * [*]) 2 test runs
rv_dm_mem_tl_access_resuming 57955306028640010475658855009422646327446799206727186713458196676552855246285 87
UVM_INFO @ 121313870 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rv_dm_stress_all 104468785191007421785174329351167302628080409440763169605907288113007820811804 91
UVM_INFO @ 2470809238 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (rv_dm_hart_unavail_vseq.sv:24) [rv_dm_hart_unavail_vseq] Check failed jtag_dmi_ral.dmstatus.anyunavail.get_mirrored_value() == req_unavailable (* [*] vs * [*]) 1 test run
rv_dm_hart_unavail 45340427769594131616943041550527663904764067387228504773302366451677766371441 87
UVM_INFO @ 54764006 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (rv_dm_jtag_dmi_debug_disabled_vseq.sv:16) [rv_dm_jtag_dmi_debug_disabled_vseq] Check failed rdata == expected_value (* [*] vs * [*]) 1 test run
rv_dm_jtag_dmi_debug_disabled 90473244527921955623326569952686105538113819065787082504547407118628856293851 87
UVM_INFO @ 622782595 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (rv_dm_scoreboard.sv:409) scoreboard [scoreboard] Unexpected response to read from address * in mem reg block. Problems: '{"Expected read d_data=*, but it was *"}. Item: (req: (cip_tl_seq_item@23866) { a_addr: * a_data: * a_mask: * a_size: * a_param: * a_source: * a_opcode: * a_user: * d_param: * d_source: * d_data: * d_size: * d_opcode: * d_error: * d_sink: * d_user: * a_valid_delay: * d_valid_delay: * a_valid_len: * d_valid_len: * req_abort_after_a_valid_len: * rsp_abort_after_d_valid_len: * req_completed: * rsp_completed: * tl_intg_err_type: TlIntgErrNone max_ecc_errors: * } 1 test run
rv_dm_rom_read_access 85809193009938252020593331938219140028356615725392000106428313854187400487126 87
).
UVM_INFO @ 153064168 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (uvm_phase.svh:1521) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue 1 test run
rv_dm_scanmode 6867171753750015243077848939107168524508613882107351133686295812059320730893 87
UVM_INFO @ 300000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---