Simulation Results: spi_device/1r1w

 
31/08/2026 21:27:41 DVSim: v1.52.0 sha: 93d21e7 json Branch: master Tool: xcelium [24.03-s007]
Coverage statistics
  • Total
  • 83.70 %
  • code
  • 89.25 %
  • assert
  • 95.27 %
  • func
  • 66.58 %
  • block
  • 98.33 %
  • line
  • 98.74 %
  • branch
  • 96.98 %
  • toggle
  • 72.75 %
  • FSM
  • 88.54 %
Validation stages
V1
100.00%
V2
92.59%
V2S
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
spi_device_flash_and_tpm 71.000s 11672.394us 1 1 100.00
csr_hw_reset 1 1 100.00
spi_device_csr_hw_reset 2.000s 207.396us 1 1 100.00
csr_rw 1 1 100.00
spi_device_csr_rw 3.000s 94.589us 1 1 100.00
csr_bit_bash 1 1 100.00
spi_device_csr_bit_bash 49.000s 9129.253us 1 1 100.00
csr_aliasing 1 1 100.00
spi_device_csr_aliasing 5.000s 755.151us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
spi_device_csr_mem_rw_with_rand_reset 4.000s 102.981us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
spi_device_csr_rw 3.000s 94.589us 1 1 100.00
spi_device_csr_aliasing 5.000s 755.151us 1 1 100.00
mem_walk 1 1 100.00
spi_device_mem_walk 1.000s 18.180us 1 1 100.00
mem_partial_access 1 1 100.00
spi_device_mem_partial_access 3.000s 476.495us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
csb_read 1 1 100.00
spi_device_csb_read 2.000s 21.795us 1 1 100.00
mem_parity 0 1 0.00
spi_device_mem_parity 2.000s 5.614us 0 1 0.00
mem_cfg 0 1 0.00
spi_device_ram_cfg 1.000s 3.434us 0 1 0.00
tpm_read 1 1 100.00
spi_device_tpm_rw 2.000s 90.471us 1 1 100.00
tpm_write 1 1 100.00
spi_device_tpm_rw 2.000s 90.471us 1 1 100.00
tpm_hw_reg 2 2 100.00
spi_device_tpm_read_hw_reg 6.000s 604.464us 1 1 100.00
spi_device_tpm_sts_read 2.000s 18.015us 1 1 100.00
tpm_fully_random_case 1 1 100.00
spi_device_tpm_all 108.000s 19730.421us 1 1 100.00
pass_cmd_filtering 2 2 100.00
spi_device_pass_cmd_filtering 69.000s 7803.198us 1 1 100.00
spi_device_flash_all 319.000s 22217.355us 1 1 100.00
pass_addr_translation 2 2 100.00
spi_device_pass_addr_payload_swap 5.000s 635.881us 1 1 100.00
spi_device_flash_all 319.000s 22217.355us 1 1 100.00
pass_payload_translation 2 2 100.00
spi_device_pass_addr_payload_swap 5.000s 635.881us 1 1 100.00
spi_device_flash_all 319.000s 22217.355us 1 1 100.00
cmd_info_slots 1 1 100.00
spi_device_flash_all 319.000s 22217.355us 1 1 100.00
cmd_read_status 2 2 100.00
spi_device_intercept 21.000s 4116.285us 1 1 100.00
spi_device_flash_all 319.000s 22217.355us 1 1 100.00
cmd_read_jedec 2 2 100.00
spi_device_intercept 21.000s 4116.285us 1 1 100.00
spi_device_flash_all 319.000s 22217.355us 1 1 100.00
cmd_read_sfdp 2 2 100.00
spi_device_intercept 21.000s 4116.285us 1 1 100.00
spi_device_flash_all 319.000s 22217.355us 1 1 100.00
cmd_fast_read 2 2 100.00
spi_device_intercept 21.000s 4116.285us 1 1 100.00
spi_device_flash_all 319.000s 22217.355us 1 1 100.00
cmd_read_pipeline 2 2 100.00
spi_device_intercept 21.000s 4116.285us 1 1 100.00
spi_device_flash_all 319.000s 22217.355us 1 1 100.00
flash_cmd_upload 1 1 100.00
spi_device_upload 47.000s 4418.645us 1 1 100.00
mailbox_command 1 1 100.00
spi_device_mailbox 20.000s 3806.655us 1 1 100.00
mailbox_cross_outside_command 1 1 100.00
spi_device_mailbox 20.000s 3806.655us 1 1 100.00
mailbox_cross_inside_command 1 1 100.00
spi_device_mailbox 20.000s 3806.655us 1 1 100.00
cmd_read_buffer 2 2 100.00
spi_device_flash_mode 4.000s 273.342us 1 1 100.00
spi_device_read_buffer_direct 8.000s 200.174us 1 1 100.00
cmd_dummy_cycle 2 2 100.00
spi_device_mailbox 20.000s 3806.655us 1 1 100.00
spi_device_flash_all 319.000s 22217.355us 1 1 100.00
quad_spi 1 1 100.00
spi_device_flash_all 319.000s 22217.355us 1 1 100.00
dual_spi 1 1 100.00
spi_device_flash_all 319.000s 22217.355us 1 1 100.00
4b_3b_feature 1 1 100.00
spi_device_cfg_cmd 7.000s 176.166us 1 1 100.00
write_enable_disable 1 1 100.00
spi_device_cfg_cmd 7.000s 176.166us 1 1 100.00
flash_mode_ignore_cmds 1 1 100.00
spi_device_flash_mode_ignore_cmds 34.000s 4420.112us 1 1 100.00
TPM_with_flash_or_passthrough_mode 1 1 100.00
spi_device_flash_and_tpm 71.000s 11672.394us 1 1 100.00
tpm_and_flash_trans_with_min_inactive_time 1 1 100.00
spi_device_flash_and_tpm_min_idle 191.000s 12537.590us 1 1 100.00
stress_all 1 1 100.00
spi_device_stress_all 103.000s 9156.214us 1 1 100.00
alert_test 1 1 100.00
spi_device_alert_test 2.000s 125.277us 1 1 100.00
intr_test 1 1 100.00
spi_device_intr_test 2.000s 13.545us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
spi_device_tl_errors 4.000s 337.959us 1 1 100.00
tl_d_illegal_access 1 1 100.00
spi_device_tl_errors 4.000s 337.959us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
spi_device_csr_hw_reset 2.000s 207.396us 1 1 100.00
spi_device_csr_rw 3.000s 94.589us 1 1 100.00
spi_device_csr_aliasing 5.000s 755.151us 1 1 100.00
spi_device_same_csr_outstanding 4.000s 260.197us 1 1 100.00
tl_d_partial_access 4 4 100.00
spi_device_csr_hw_reset 2.000s 207.396us 1 1 100.00
spi_device_csr_rw 3.000s 94.589us 1 1 100.00
spi_device_csr_aliasing 5.000s 755.151us 1 1 100.00
spi_device_same_csr_outstanding 4.000s 260.197us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
spi_device_sec_cm 3.000s 399.734us 1 1 100.00
spi_device_tl_intg_err 11.000s 756.659us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
spi_device_tl_intg_err 11.000s 756.659us 1 1 100.00

Error Messages

   Test seed line log context
UVM_ERROR (uvm_hdl_inca.c:743) [UVM/DPI/NOBJ1] name tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.mem[*] cannot be resolved to a hdl object (vlog,vhdl,vlog-slice) 1 test run
spi_device_mem_parity 85439343539261773249637201554367557039765282474211536733251078117350792698949 87
UVM_ERROR @ 3214424 ps: (spi_device_mem_parity_vseq.sv:44) [uvm_test_top.env.virtual_sequencer.spi_device_mem_parity_vseq] Check failed (uvm_hdl_read(egress_path, mem_data))
ERROR: VHPI NOTFOUND
Name tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.mem[907] not found within the scope .
UVM_ERROR @ 3214424 ps: (uvm_hdl_inca.c:743) [UVM/DPI/NOBJ2] name tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.mem[907] cannot be resolved to a hdl object (vlog,vhdl,vlog-slice)
UVM_ERROR (spi_device_ram_cfg_vseq.sv:28) [spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (* [*] vs * [*]) 1 test run
spi_device_ram_cfg 4092975803086118319384005566375464087500509040911717489943929250021078828251 85
UVM_ERROR @ 1270958 ps: (spi_device_ram_cfg_vseq.sv:28) [uvm_test_top.env.virtual_sequencer.spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (0x3f8 [1111111000] vs 0x0 [0])
UVM_ERROR @ 1297958 ps: (spi_device_ram_cfg_vseq.sv:28) [uvm_test_top.env.virtual_sequencer.spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (0x24e [1001001110] vs 0x0 [0])
UVM_ERROR @ 1320958 ps: (spi_device_ram_cfg_vseq.sv:28) [uvm_test_top.env.virtual_sequencer.spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (0x3e9 [1111101001] vs 0x0 [0])
UVM_ERROR @ 1391958 ps: (spi_device_ram_cfg_vseq.sv:28) [uvm_test_top.env.virtual_sequencer.spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (0x308 [1100001000] vs 0x0 [0])