Simulation Results: sram_ctrl/main

 
31/08/2026 21:27:41 DVSim: v1.52.0 sha: 93d21e7 json Branch: master Tool: xcelium [24.03-s007]
Coverage statistics
  • Total
  • 95.21 %
  • code
  • 95.09 %
  • assert
  • 97.96 %
  • func
  • 92.60 %
  • block
  • 94.48 %
  • line
  • 95.64 %
  • branch
  • 92.86 %
  • toggle
  • 91.84 %
  • FSM
  • 100.00 %
Validation stages
V1
100.00%
V2
100.00%
V2S
80.00%
V3
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
sram_ctrl_smoke 5.000s 682.443us 1 1 100.00
csr_hw_reset 1 1 100.00
sram_ctrl_csr_hw_reset 1.000s 17.013us 1 1 100.00
csr_rw 1 1 100.00
sram_ctrl_csr_rw 2.000s 37.783us 1 1 100.00
csr_bit_bash 1 1 100.00
sram_ctrl_csr_bit_bash 3.000s 250.140us 1 1 100.00
csr_aliasing 1 1 100.00
sram_ctrl_csr_aliasing 2.000s 52.630us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
sram_ctrl_csr_mem_rw_with_rand_reset 3.000s 384.274us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
sram_ctrl_csr_rw 2.000s 37.783us 1 1 100.00
sram_ctrl_csr_aliasing 2.000s 52.630us 1 1 100.00
mem_walk 1 1 100.00
sram_ctrl_mem_walk 168.000s 13697.004us 1 1 100.00
mem_partial_access 1 1 100.00
sram_ctrl_mem_partial_access 70.000s 5291.493us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
multiple_keys 1 1 100.00
sram_ctrl_multiple_keys 40.000s 32226.069us 1 1 100.00
stress_pipeline 1 1 100.00
sram_ctrl_stress_pipeline 168.000s 7140.938us 1 1 100.00
bijection 1 1 100.00
sram_ctrl_bijection 167.000s 16407.085us 1 1 100.00
access_during_key_req 1 1 100.00
sram_ctrl_access_during_key_req 88.000s 84511.599us 1 1 100.00
lc_escalation 1 1 100.00
sram_ctrl_lc_escalation 26.000s 15788.841us 1 1 100.00
executable 1 1 100.00
sram_ctrl_executable 55.000s 14098.786us 1 1 100.00
partial_access 2 2 100.00
sram_ctrl_partial_access 4.000s 1560.269us 1 1 100.00
sram_ctrl_partial_access_b2b 132.000s 9142.214us 1 1 100.00
max_throughput 3 3 100.00
sram_ctrl_max_throughput 6.000s 675.490us 1 1 100.00
sram_ctrl_throughput_w_partial_write 6.000s 1307.727us 1 1 100.00
sram_ctrl_throughput_w_readback 4.000s 1354.657us 1 1 100.00
regwen 1 1 100.00
sram_ctrl_regwen 6.000s 1764.857us 1 1 100.00
ram_cfg 1 1 100.00
sram_ctrl_ram_cfg 4.000s 693.700us 1 1 100.00
non_pow2_mem_size 3 3 100.00
sram_ctrl_smoke 5.000s 682.443us 1 1 100.00
sram_ctrl_partial_access 4.000s 1560.269us 1 1 100.00
sram_ctrl_access_during_key_req 88.000s 84511.599us 1 1 100.00
stress_all 1 1 100.00
sram_ctrl_stress_all 171.000s 144988.215us 1 1 100.00
alert_test 1 1 100.00
sram_ctrl_alert_test 1.000s 34.180us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
sram_ctrl_tl_errors 4.000s 453.793us 1 1 100.00
tl_d_illegal_access 1 1 100.00
sram_ctrl_tl_errors 4.000s 453.793us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
sram_ctrl_csr_hw_reset 1.000s 17.013us 1 1 100.00
sram_ctrl_csr_rw 2.000s 37.783us 1 1 100.00
sram_ctrl_csr_aliasing 2.000s 52.630us 1 1 100.00
sram_ctrl_same_csr_outstanding 1.000s 24.716us 1 1 100.00
tl_d_partial_access 4 4 100.00
sram_ctrl_csr_hw_reset 1.000s 17.013us 1 1 100.00
sram_ctrl_csr_rw 2.000s 37.783us 1 1 100.00
sram_ctrl_csr_aliasing 2.000s 52.630us 1 1 100.00
sram_ctrl_same_csr_outstanding 1.000s 24.716us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
passthru_mem_tl_intg_err 1 1 100.00
sram_ctrl_passthru_mem_tl_intg_err 28.000s 7955.734us 1 1 100.00
tl_intg_err 2 2 100.00
sram_ctrl_sec_cm 3.000s 1329.905us 1 1 100.00
sram_ctrl_tl_intg_err 2.000s 747.144us 1 1 100.00
prim_count_check 1 1 100.00
sram_ctrl_sec_cm 3.000s 1329.905us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
sram_ctrl_tl_intg_err 2.000s 747.144us 1 1 100.00
sec_cm_ctrl_config_regwen 1 1 100.00
sram_ctrl_regwen 6.000s 1764.857us 1 1 100.00
sec_cm_readback_config_regwen 1 1 100.00
sram_ctrl_regwen 6.000s 1764.857us 1 1 100.00
sec_cm_exec_config_regwen 1 1 100.00
sram_ctrl_csr_rw 2.000s 37.783us 1 1 100.00
sec_cm_exec_config_mubi 1 1 100.00
sram_ctrl_executable 55.000s 14098.786us 1 1 100.00
sec_cm_exec_intersig_mubi 1 1 100.00
sram_ctrl_executable 55.000s 14098.786us 1 1 100.00
sec_cm_lc_hw_debug_en_intersig_mubi 1 1 100.00
sram_ctrl_executable 55.000s 14098.786us 1 1 100.00
sec_cm_lc_escalate_en_intersig_mubi 1 1 100.00
sram_ctrl_lc_escalation 26.000s 15788.841us 1 1 100.00
sec_cm_prim_ram_ctrl_mubi 0 1 0.00
sram_ctrl_mubi_enc_err 3600.000s 0.000us 0 1 0.00
sec_cm_mem_integrity 1 1 100.00
sram_ctrl_passthru_mem_tl_intg_err 28.000s 7955.734us 1 1 100.00
sec_cm_mem_readback 0 1 0.00
sram_ctrl_readback_err 3600.000s 0.000us 0 1 0.00
sec_cm_mem_scramble 1 1 100.00
sram_ctrl_smoke 5.000s 682.443us 1 1 100.00
sec_cm_addr_scramble 1 1 100.00
sram_ctrl_smoke 5.000s 682.443us 1 1 100.00
sec_cm_instr_bus_lc_gated 1 1 100.00
sram_ctrl_executable 55.000s 14098.786us 1 1 100.00
sec_cm_ram_tl_lc_gate_fsm_sparse 1 1 100.00
sram_ctrl_sec_cm 3.000s 1329.905us 1 1 100.00
sec_cm_key_global_esc 1 1 100.00
sram_ctrl_lc_escalation 26.000s 15788.841us 1 1 100.00
sec_cm_key_local_esc 1 1 100.00
sram_ctrl_sec_cm 3.000s 1329.905us 1 1 100.00
sec_cm_init_ctr_redun 1 1 100.00
sram_ctrl_sec_cm 3.000s 1329.905us 1 1 100.00
sec_cm_scramble_key_sideload 1 1 100.00
sram_ctrl_smoke 5.000s 682.443us 1 1 100.00
sec_cm_tlul_fifo_ctr_redun 1 1 100.00
sram_ctrl_sec_cm 3.000s 1329.905us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 1 1 100.00
sram_ctrl_stress_all_with_rand_reset 16.000s 1240.159us 1 1 100.00

Error Messages

   Test seed line log context
Job timed out after * minutes 2 test runs
sram_ctrl_readback_err 18690092553428347302789215089446249117924868164672853306449575981841631090039 None
sram_ctrl_mubi_enc_err 63447804016135058501156570285917868555302132184829876910654000724762471750463 None