Simulation Results: sram_ctrl/ret

 
31/08/2026 21:27:41 DVSim: v1.52.0 sha: 93d21e7 json Branch: master Tool: xcelium [24.03-s007]
Coverage statistics
  • Total
  • 91.50 %
  • code
  • 81.75 %
  • assert
  • 97.95 %
  • func
  • 94.80 %
  • block
  • 92.19 %
  • line
  • 93.78 %
  • branch
  • 88.23 %
  • toggle
  • 78.32 %
  • FSM
  • 66.67 %
Validation stages
V1
87.50%
V2
100.00%
V2S
80.00%
V3
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
sram_ctrl_smoke 2.000s 37.751us 1 1 100.00
csr_hw_reset 1 1 100.00
sram_ctrl_csr_hw_reset 2.000s 45.298us 1 1 100.00
csr_rw 1 1 100.00
sram_ctrl_csr_rw 1.000s 13.940us 1 1 100.00
csr_bit_bash 1 1 100.00
sram_ctrl_csr_bit_bash 4.000s 1049.976us 1 1 100.00
csr_aliasing 1 1 100.00
sram_ctrl_csr_aliasing 2.000s 30.864us 1 1 100.00
csr_mem_rw_with_rand_reset 0 1 0.00
sram_ctrl_csr_mem_rw_with_rand_reset 2.000s 52.134us 0 1 0.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
sram_ctrl_csr_rw 1.000s 13.940us 1 1 100.00
sram_ctrl_csr_aliasing 2.000s 30.864us 1 1 100.00
mem_walk 1 1 100.00
sram_ctrl_mem_walk 10.000s 1255.011us 1 1 100.00
mem_partial_access 1 1 100.00
sram_ctrl_mem_partial_access 4.000s 104.448us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
multiple_keys 1 1 100.00
sram_ctrl_multiple_keys 11.000s 1102.793us 1 1 100.00
stress_pipeline 1 1 100.00
sram_ctrl_stress_pipeline 159.000s 8965.124us 1 1 100.00
bijection 1 1 100.00
sram_ctrl_bijection 10.000s 6935.066us 1 1 100.00
access_during_key_req 1 1 100.00
sram_ctrl_access_during_key_req 18.000s 594.684us 1 1 100.00
lc_escalation 1 1 100.00
sram_ctrl_lc_escalation 8.000s 798.603us 1 1 100.00
executable 1 1 100.00
sram_ctrl_executable 15.000s 3609.286us 1 1 100.00
partial_access 2 2 100.00
sram_ctrl_partial_access 2.000s 30.235us 1 1 100.00
sram_ctrl_partial_access_b2b 253.000s 57195.348us 1 1 100.00
max_throughput 3 3 100.00
sram_ctrl_max_throughput 2.000s 71.779us 1 1 100.00
sram_ctrl_throughput_w_partial_write 1.000s 141.964us 1 1 100.00
sram_ctrl_throughput_w_readback 2.000s 44.884us 1 1 100.00
regwen 1 1 100.00
sram_ctrl_regwen 6.000s 426.492us 1 1 100.00
ram_cfg 1 1 100.00
sram_ctrl_ram_cfg 2.000s 46.961us 1 1 100.00
non_pow2_mem_size 3 3 100.00
sram_ctrl_smoke 2.000s 37.751us 1 1 100.00
sram_ctrl_partial_access 2.000s 30.235us 1 1 100.00
sram_ctrl_access_during_key_req 18.000s 594.684us 1 1 100.00
stress_all 1 1 100.00
sram_ctrl_stress_all 24.000s 2228.068us 1 1 100.00
alert_test 1 1 100.00
sram_ctrl_alert_test 1.000s 11.622us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
sram_ctrl_tl_errors 6.000s 510.500us 1 1 100.00
tl_d_illegal_access 1 1 100.00
sram_ctrl_tl_errors 6.000s 510.500us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
sram_ctrl_csr_hw_reset 2.000s 45.298us 1 1 100.00
sram_ctrl_csr_rw 1.000s 13.940us 1 1 100.00
sram_ctrl_csr_aliasing 2.000s 30.864us 1 1 100.00
sram_ctrl_same_csr_outstanding 1.000s 26.322us 1 1 100.00
tl_d_partial_access 4 4 100.00
sram_ctrl_csr_hw_reset 2.000s 45.298us 1 1 100.00
sram_ctrl_csr_rw 1.000s 13.940us 1 1 100.00
sram_ctrl_csr_aliasing 2.000s 30.864us 1 1 100.00
sram_ctrl_same_csr_outstanding 1.000s 26.322us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
passthru_mem_tl_intg_err 1 1 100.00
sram_ctrl_passthru_mem_tl_intg_err 3.000s 352.502us 1 1 100.00
tl_intg_err 2 2 100.00
sram_ctrl_sec_cm 4.000s 1244.742us 1 1 100.00
sram_ctrl_tl_intg_err 2.000s 268.892us 1 1 100.00
prim_count_check 1 1 100.00
sram_ctrl_sec_cm 4.000s 1244.742us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
sram_ctrl_tl_intg_err 2.000s 268.892us 1 1 100.00
sec_cm_ctrl_config_regwen 1 1 100.00
sram_ctrl_regwen 6.000s 426.492us 1 1 100.00
sec_cm_readback_config_regwen 1 1 100.00
sram_ctrl_regwen 6.000s 426.492us 1 1 100.00
sec_cm_exec_config_regwen 1 1 100.00
sram_ctrl_csr_rw 1.000s 13.940us 1 1 100.00
sec_cm_exec_config_mubi 1 1 100.00
sram_ctrl_executable 15.000s 3609.286us 1 1 100.00
sec_cm_exec_intersig_mubi 1 1 100.00
sram_ctrl_executable 15.000s 3609.286us 1 1 100.00
sec_cm_lc_hw_debug_en_intersig_mubi 1 1 100.00
sram_ctrl_executable 15.000s 3609.286us 1 1 100.00
sec_cm_lc_escalate_en_intersig_mubi 1 1 100.00
sram_ctrl_lc_escalation 8.000s 798.603us 1 1 100.00
sec_cm_prim_ram_ctrl_mubi 0 1 0.00
sram_ctrl_mubi_enc_err 3600.000s 0.000us 0 1 0.00
sec_cm_mem_integrity 1 1 100.00
sram_ctrl_passthru_mem_tl_intg_err 3.000s 352.502us 1 1 100.00
sec_cm_mem_readback 0 1 0.00
sram_ctrl_readback_err 3600.000s 0.000us 0 1 0.00
sec_cm_mem_scramble 1 1 100.00
sram_ctrl_smoke 2.000s 37.751us 1 1 100.00
sec_cm_addr_scramble 1 1 100.00
sram_ctrl_smoke 2.000s 37.751us 1 1 100.00
sec_cm_instr_bus_lc_gated 1 1 100.00
sram_ctrl_executable 15.000s 3609.286us 1 1 100.00
sec_cm_ram_tl_lc_gate_fsm_sparse 1 1 100.00
sram_ctrl_sec_cm 4.000s 1244.742us 1 1 100.00
sec_cm_key_global_esc 1 1 100.00
sram_ctrl_lc_escalation 8.000s 798.603us 1 1 100.00
sec_cm_key_local_esc 1 1 100.00
sram_ctrl_sec_cm 4.000s 1244.742us 1 1 100.00
sec_cm_init_ctr_redun 1 1 100.00
sram_ctrl_sec_cm 4.000s 1244.742us 1 1 100.00
sec_cm_scramble_key_sideload 1 1 100.00
sram_ctrl_smoke 2.000s 37.751us 1 1 100.00
sec_cm_tlul_fifo_ctr_redun 1 1 100.00
sram_ctrl_sec_cm 4.000s 1244.742us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 1 1 100.00
sram_ctrl_stress_all_with_rand_reset 16.000s 719.334us 1 1 100.00

Error Messages

   Test seed line log context
Job timed out after * minutes 2 test runs
sram_ctrl_readback_err 34983560431757331938325113690886759672679276046748326988751523510257716333670 None
sram_ctrl_mubi_enc_err 108613266332223913924109438966291078039734426106208719174805211011448490328797 None
UVM_ERROR (csr_utils_pkg.sv:463) [csr_utils_pkg::csr_rd_check.isolation_fork.unmblk1] Check failed obs == exp (* [*] vs * [*]) Regname: sram_ctrl_regs_reg_block.status reset value: * 1 test run
sram_ctrl_csr_mem_rw_with_rand_reset 47084584250770930434678244357444315177831548540655668998395636453164389162712 88
UVM_INFO @ 52133645 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---