Simulation Results

Simulation Results: uart

31/08/2026 21:27:41 DVSim: v1.52.0 sha: 93d21e7 json Branch: master Tool: xcelium [24.03-s007]

Coverage statistics

Total
94.00 %

code
92.73 %

assert
98.56 %

func
90.69 %

block
99.08 %

line
99.52 %

branch
98.34 %

toggle
73.08 %

FSM
100.00 %

Validation stages

V1		100.00%
V2		95.45%
V2S		100.00%
V3		0.00%

6/6 passed

100.00 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
smoke				1	1	100.00
	uart_smoke	2.000s	289.891us	1	1	100.00
csr_hw_reset				1	1	100.00
	uart_csr_hw_reset	1.000s	14.976us	1	1	100.00
csr_rw				1	1	100.00
	uart_csr_rw	1.000s	29.896us	1	1	100.00
csr_bit_bash				1	1	100.00
	uart_csr_bit_bash	3.000s	129.833us	1	1	100.00
csr_aliasing				1	1	100.00
	uart_csr_aliasing	2.000s	44.012us	1	1	100.00
csr_mem_rw_with_rand_reset				1	1	100.00
	uart_csr_mem_rw_with_rand_reset	1.000s	22.692us	1	1	100.00
regwen_csr_and_corresponding_lockable_csr				2	2	100.00
	uart_csr_rw	1.000s	29.896us	1	1	100.00
	uart_csr_aliasing	2.000s	44.012us	1	1	100.00

21/22 passed

95.45 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
base_random_seq				1	1	100.00
	uart_tx_rx	18.000s	21600.864us	1	1	100.00
parity				2	2	100.00
	uart_smoke	2.000s	289.891us	1	1	100.00
	uart_tx_rx	18.000s	21600.864us	1	1	100.00
parity_error				2	2	100.00
	uart_intr	30.000s	20609.698us	1	1	100.00
	uart_rx_parity_err	33.000s	14240.838us	1	1	100.00
watermark				2	2	100.00
	uart_tx_rx	18.000s	21600.864us	1	1	100.00
	uart_intr	30.000s	20609.698us	1	1	100.00
fifo_full				1	1	100.00
	uart_fifo_full	14.000s	21189.492us	1	1	100.00
fifo_overflow				1	1	100.00
	uart_fifo_overflow	188.000s	183325.398us	1	1	100.00
fifo_reset				1	1	100.00
	uart_fifo_reset	46.000s	96503.540us	1	1	100.00
rx_frame_err				1	1	100.00
	uart_intr	30.000s	20609.698us	1	1	100.00
rx_break_err				1	1	100.00
	uart_intr	30.000s	20609.698us	1	1	100.00
rx_timeout				1	1	100.00
	uart_intr	30.000s	20609.698us	1	1	100.00
perf				1	1	100.00
	uart_perf	113.000s	18668.666us	1	1	100.00
sys_loopback				1	1	100.00
	uart_loopback	7.000s	4757.516us	1	1	100.00
line_loopback				1	1	100.00
	uart_loopback	7.000s	4757.516us	1	1	100.00
rx_noise_filter				0	1	0.00
	uart_noise_filter	10.000s	3395.298us	0	1	0.00
rx_start_bit_filter				1	1	100.00
	uart_rx_start_bit_filter	2.000s	3979.249us	1	1	100.00
tx_overide				1	1	100.00
	uart_tx_ovrd	26.000s	6294.400us	1	1	100.00
rx_oversample				1	1	100.00
	uart_rx_oversample	31.000s	4317.716us	1	1	100.00
long_b2b_transfer				1	1	100.00
	uart_long_xfer_wo_dly	301.000s	180569.076us	1	1	100.00
stress_all				1	1	100.00
	uart_stress_all	271.000s	287457.956us	1	1	100.00
alert_test				1	1	100.00
	uart_alert_test	1.000s	23.907us	1	1	100.00
intr_test				1	1	100.00
	uart_intr_test	1.000s	186.531us	1	1	100.00
tl_d_oob_addr_access				1	1	100.00
	uart_tl_errors	3.000s	126.116us	1	1	100.00
tl_d_illegal_access				1	1	100.00
	uart_tl_errors	3.000s	126.116us	1	1	100.00
tl_d_outstanding_access				4	4	100.00
	uart_csr_hw_reset	1.000s	14.976us	1	1	100.00
	uart_csr_rw	1.000s	29.896us	1	1	100.00
	uart_csr_aliasing	2.000s	44.012us	1	1	100.00
	uart_same_csr_outstanding	2.000s	58.828us	1	1	100.00
tl_d_partial_access				4	4	100.00
	uart_csr_hw_reset	1.000s	14.976us	1	1	100.00
	uart_csr_rw	1.000s	29.896us	1	1	100.00
	uart_csr_aliasing	2.000s	44.012us	1	1	100.00
	uart_same_csr_outstanding	2.000s	58.828us	1	1	100.00

V2S

2/2 passed

100.00 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
tl_intg_err				2	2	100.00
	uart_sec_cm	1.000s	141.987us	1	1	100.00
	uart_tl_intg_err	2.000s	221.931us	1	1	100.00
sec_cm_bus_integrity				1	1	100.00
	uart_tl_intg_err	2.000s	221.931us	1	1	100.00

0/1 passed

0.00 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
stress_all_with_rand_reset				0	1	0.00
	uart_stress_all_with_rand_reset	24.000s	7237.188us	0	1	0.00

Error Messages

	Test	seed	line	log context
UVM_ERROR (uart_scoreboard.sv:392) [scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (* [] vs []) check rx_idle fail: rx_en = , uart_rx_clk_pulses = *				2 test runs
	uart_noise_filter	113281315596451462972754363458374088231618929063242006652033581091750519618269	87	UVM_ERROR @ 3348629558 ps: (uart_scoreboard.sv:392) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0 UVM_ERROR @ 3349670767 ps: (uart_scoreboard.sv:392) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0 UVM_ERROR @ 3350598577 ps: (uart_scoreboard.sv:392) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0 UVM_ERROR @ 3351526387 ps: (uart_scoreboard.sv:392) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0
	uart_stress_all_with_rand_reset	49212506435429979019215644814569554737907724400797514343883512621003215488118	189	UVM_ERROR @ 6704066371 ps: (csr_utils_pkg.sv:463) [csr_utils_pkg::csr_rd_check.isolation_fork.unmblk1] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: uart_reg_block.status.rxidle reset value: 0x1 UVM_INFO @ 6724203355 ps: (cip_base_vseq.sv:1213) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_common_vseq] Issuing reset for run 8/10 UVM_INFO @ 6724549513 ps: (cip_base_vseq.sv:1234) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_common_vseq]