Simulation Results: aes/gcm_masked

 
01/09/2026 21:34:42 DVSim: v1.52.0 sha: 4e5c99d json Branch: master Tool: xcelium [24.03-s007]
Coverage statistics
  • Total
  • 86.88 %
  • code
  • 95.55 %
  • assert
  • 98.43 %
  • func
  • 66.67 %
  • block
  • 96.26 %
  • line
  • 97.46 %
  • branch
  • 91.19 %
  • toggle
  • 98.05 %
  • FSM
  • 95.48 %
Validation stages
V1
100.00%
V2
94.74%
V2S
88.89%
V3
0.00%
Testpoint Test Max Runtime Sim Time Pass Total %
wake_up 1 1 100.00
aes_wake_up 3.000s 126.306us 1 1 100.00
smoke 1 1 100.00
aes_smoke 4.000s 144.385us 1 1 100.00
csr_hw_reset 1 1 100.00
aes_csr_hw_reset 2.000s 69.251us 1 1 100.00
csr_rw 1 1 100.00
aes_csr_rw 1.000s 166.799us 1 1 100.00
csr_bit_bash 1 1 100.00
aes_csr_bit_bash 6.000s 249.057us 1 1 100.00
csr_aliasing 1 1 100.00
aes_csr_aliasing 2.000s 120.796us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
aes_csr_mem_rw_with_rand_reset 2.000s 98.975us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
aes_csr_rw 1.000s 166.799us 1 1 100.00
aes_csr_aliasing 2.000s 120.796us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
algorithm 3 3 100.00
aes_smoke 4.000s 144.385us 1 1 100.00
aes_config_error 5.000s 396.132us 1 1 100.00
aes_stress 3.000s 170.898us 1 1 100.00
key_length 3 3 100.00
aes_smoke 4.000s 144.385us 1 1 100.00
aes_config_error 5.000s 396.132us 1 1 100.00
aes_stress 3.000s 170.898us 1 1 100.00
back2back 2 2 100.00
aes_stress 3.000s 170.898us 1 1 100.00
aes_b2b 14.000s 1915.843us 1 1 100.00
backpressure 1 1 100.00
aes_stress 3.000s 170.898us 1 1 100.00
multi_message 4 4 100.00
aes_smoke 4.000s 144.385us 1 1 100.00
aes_config_error 5.000s 396.132us 1 1 100.00
aes_stress 3.000s 170.898us 1 1 100.00
aes_alert_reset 2.000s 187.216us 1 1 100.00
failure_test 3 3 100.00
aes_man_cfg_err 3.000s 113.921us 1 1 100.00
aes_config_error 5.000s 396.132us 1 1 100.00
aes_alert_reset 2.000s 187.216us 1 1 100.00
trigger_clear_test 1 1 100.00
aes_clear 3.000s 173.297us 1 1 100.00
nist_test_vectors 1 1 100.00
aes_nist_vectors 16.000s 917.959us 1 1 100.00
nist_test_vectors_gcm 1 1 100.00
aes_nist_vectors_gcm 10.000s 1651.949us 1 1 100.00
reset_recovery 1 1 100.00
aes_alert_reset 2.000s 187.216us 1 1 100.00
stress 1 1 100.00
aes_stress 3.000s 170.898us 1 1 100.00
sideload 2 2 100.00
aes_stress 3.000s 170.898us 1 1 100.00
aes_sideload 4.000s 166.978us 1 1 100.00
deinitialization 1 1 100.00
aes_deinit 5.000s 195.738us 1 1 100.00
stress_all 0 1 0.00
aes_stress_all 13.000s 167.216us 0 1 0.00
gcm_save_and_restore 1 1 100.00
aes_gcm_save_restore 5.000s 135.391us 1 1 100.00
alert_test 1 1 100.00
aes_alert_test 2.000s 53.310us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
aes_tl_errors 3.000s 91.378us 1 1 100.00
tl_d_illegal_access 1 1 100.00
aes_tl_errors 3.000s 91.378us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
aes_csr_hw_reset 2.000s 69.251us 1 1 100.00
aes_csr_rw 1.000s 166.799us 1 1 100.00
aes_csr_aliasing 2.000s 120.796us 1 1 100.00
aes_same_csr_outstanding 3.000s 105.109us 1 1 100.00
tl_d_partial_access 4 4 100.00
aes_csr_hw_reset 2.000s 69.251us 1 1 100.00
aes_csr_rw 1.000s 166.799us 1 1 100.00
aes_csr_aliasing 2.000s 120.796us 1 1 100.00
aes_same_csr_outstanding 3.000s 105.109us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
reseeding 0 1 0.00
aes_reseed 5.000s 47.785us 0 1 0.00
fault_inject 2 3 66.67
aes_fi 8.000s 124.095us 0 1 0.00
aes_control_fi 3.000s 92.495us 1 1 100.00
aes_cipher_fi 3.000s 49.831us 1 1 100.00
shadow_reg_update_error 1 1 100.00
aes_shadow_reg_errors 3.000s 333.445us 1 1 100.00
shadow_reg_read_clear_staged_value 1 1 100.00
aes_shadow_reg_errors 3.000s 333.445us 1 1 100.00
shadow_reg_storage_error 1 1 100.00
aes_shadow_reg_errors 3.000s 333.445us 1 1 100.00
shadowed_reset_glitch 1 1 100.00
aes_shadow_reg_errors 3.000s 333.445us 1 1 100.00
shadow_reg_update_error_with_csr_rw 1 1 100.00
aes_shadow_reg_errors_with_csr_rw 5.000s 528.219us 1 1 100.00
tl_intg_err 2 2 100.00
aes_sec_cm 4.000s 1035.117us 1 1 100.00
aes_tl_intg_err 3.000s 190.338us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
aes_tl_intg_err 3.000s 190.338us 1 1 100.00
sec_cm_lc_escalate_en_intersig_mubi 1 1 100.00
aes_alert_reset 2.000s 187.216us 1 1 100.00
sec_cm_main_config_shadow 1 1 100.00
aes_shadow_reg_errors 3.000s 333.445us 1 1 100.00
sec_cm_gcm_config_shadow 1 1 100.00
aes_shadow_reg_errors 3.000s 333.445us 1 1 100.00
sec_cm_main_config_sparse 4 4 100.00
aes_smoke 4.000s 144.385us 1 1 100.00
aes_stress 3.000s 170.898us 1 1 100.00
aes_alert_reset 2.000s 187.216us 1 1 100.00
aes_core_fi 4.000s 165.170us 1 1 100.00
sec_cm_gcm_config_sparse 4 4 100.00
aes_gcm_save_restore 5.000s 135.391us 1 1 100.00
aes_config_error 5.000s 396.132us 1 1 100.00
aes_stress 3.000s 170.898us 1 1 100.00
aes_core_fi 4.000s 165.170us 1 1 100.00
sec_cm_aux_config_shadow 1 1 100.00
aes_shadow_reg_errors 3.000s 333.445us 1 1 100.00
sec_cm_aux_config_regwen 2 2 100.00
aes_readability 3.000s 182.690us 1 1 100.00
aes_stress 3.000s 170.898us 1 1 100.00
sec_cm_key_sideload 2 2 100.00
aes_stress 3.000s 170.898us 1 1 100.00
aes_sideload 4.000s 166.978us 1 1 100.00
sec_cm_key_sw_unreadable 1 1 100.00
aes_readability 3.000s 182.690us 1 1 100.00
sec_cm_data_reg_sw_unreadable 1 1 100.00
aes_readability 3.000s 182.690us 1 1 100.00
sec_cm_key_sec_wipe 1 1 100.00
aes_readability 3.000s 182.690us 1 1 100.00
sec_cm_iv_config_sec_wipe 1 1 100.00
aes_readability 3.000s 182.690us 1 1 100.00
sec_cm_data_reg_sec_wipe 1 1 100.00
aes_readability 3.000s 182.690us 1 1 100.00
sec_cm_data_reg_key_sca 1 1 100.00
aes_stress 3.000s 170.898us 1 1 100.00
sec_cm_key_masking 1 1 100.00
aes_stress 3.000s 170.898us 1 1 100.00
sec_cm_main_fsm_sparse 0 1 0.00
aes_fi 8.000s 124.095us 0 1 0.00
sec_cm_main_fsm_redun 3 4 75.00
aes_fi 8.000s 124.095us 0 1 0.00
aes_control_fi 3.000s 92.495us 1 1 100.00
aes_cipher_fi 3.000s 49.831us 1 1 100.00
aes_ctr_fi 2.000s 126.499us 1 1 100.00
sec_cm_cipher_fsm_sparse 0 1 0.00
aes_fi 8.000s 124.095us 0 1 0.00
sec_cm_cipher_fsm_redun 2 3 66.67
aes_fi 8.000s 124.095us 0 1 0.00
aes_control_fi 3.000s 92.495us 1 1 100.00
aes_cipher_fi 3.000s 49.831us 1 1 100.00
sec_cm_cipher_ctr_redun 1 1 100.00
aes_cipher_fi 3.000s 49.831us 1 1 100.00
sec_cm_ctr_fsm_sparse 0 1 0.00
aes_fi 8.000s 124.095us 0 1 0.00
sec_cm_ctr_fsm_redun 2 3 66.67
aes_fi 8.000s 124.095us 0 1 0.00
aes_control_fi 3.000s 92.495us 1 1 100.00
aes_ctr_fi 2.000s 126.499us 1 1 100.00
sec_cm_ghash_fsm_sparse 0 1 0.00
aes_fi 8.000s 124.095us 0 1 0.00
sec_cm_ctrl_sparse 3 4 75.00
aes_fi 8.000s 124.095us 0 1 0.00
aes_control_fi 3.000s 92.495us 1 1 100.00
aes_cipher_fi 3.000s 49.831us 1 1 100.00
aes_ctr_fi 2.000s 126.499us 1 1 100.00
sec_cm_main_fsm_global_esc 1 1 100.00
aes_alert_reset 2.000s 187.216us 1 1 100.00
sec_cm_main_fsm_local_esc 3 4 75.00
aes_fi 8.000s 124.095us 0 1 0.00
aes_control_fi 3.000s 92.495us 1 1 100.00
aes_cipher_fi 3.000s 49.831us 1 1 100.00
aes_ctr_fi 2.000s 126.499us 1 1 100.00
sec_cm_cipher_fsm_local_esc 3 4 75.00
aes_fi 8.000s 124.095us 0 1 0.00
aes_control_fi 3.000s 92.495us 1 1 100.00
aes_cipher_fi 3.000s 49.831us 1 1 100.00
aes_ctr_fi 2.000s 126.499us 1 1 100.00
sec_cm_ctr_fsm_local_esc 2 3 66.67
aes_fi 8.000s 124.095us 0 1 0.00
aes_control_fi 3.000s 92.495us 1 1 100.00
aes_ctr_fi 2.000s 126.499us 1 1 100.00
sec_cm_ghash_fsm_local_esc 1 2 50.00
aes_ghash_fi 2.000s 52.626us 1 1 100.00
aes_fi 8.000s 124.095us 0 1 0.00
sec_cm_data_reg_local_esc 2 3 66.67
aes_fi 8.000s 124.095us 0 1 0.00
aes_control_fi 3.000s 92.495us 1 1 100.00
aes_cipher_fi 3.000s 49.831us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 0 1 0.00
aes_stress_all_with_rand_reset 4.000s 32.250us 0 1 0.00

Error Messages

   Test seed line log context
UVM_ERROR (uvm_sequencer_base.svh:757) sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'sequencer' for sequence 'parent_sequence' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues 3 test runs
aes_reseed 14161091484054152016056912681958437391230009744181597400490998758158859119838 7973
UVM_INFO @ 47785463 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
aes_stress_all 43248770810255238356997214522760560046656044180383555805274399732489915999851 41281
UVM_INFO @ 167216494 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
aes_stress_all_with_rand_reset 93980072196657191404313989365508313987526418553164112328501305191269767447628 173
UVM_INFO @ 32249640 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (aes_scoreboard.sv:923) scoreboard [scoreboard] 1 test run
aes_fi 57050722375493277698770114229895186897342356596756579590711870082659938141858 21664
----| NO FAILURES BUT NUMBER OF EXPECTED MESSAGES DOES NOT MATCH ACTUAL
----| Expected: 5
----| Seen: 4
----| Expected corrupted: 0