Simulation Results: aes/gcm_unmasked

 
01/09/2026 21:34:42 DVSim: v1.52.0 sha: 4e5c99d json Branch: master Tool: xcelium [24.03-s007]
Coverage statistics
  • Total
  • 84.36 %
  • code
  • 90.94 %
  • assert
  • 97.94 %
  • func
  • 64.20 %
  • block
  • 90.39 %
  • line
  • 92.36 %
  • branch
  • 82.62 %
  • toggle
  • 97.99 %
  • FSM
  • 90.78 %
Validation stages
V1
100.00%
V2
94.12%
V2S
93.75%
V3
0.00%
Testpoint Test Max Runtime Sim Time Pass Total %
wake_up 1 1 100.00
aes_wake_up 2.000s 94.695us 1 1 100.00
smoke 1 1 100.00
aes_smoke 2.000s 85.643us 1 1 100.00
csr_hw_reset 1 1 100.00
aes_csr_hw_reset 1.000s 106.401us 1 1 100.00
csr_rw 1 1 100.00
aes_csr_rw 1.000s 60.003us 1 1 100.00
csr_bit_bash 1 1 100.00
aes_csr_bit_bash 5.000s 253.214us 1 1 100.00
csr_aliasing 1 1 100.00
aes_csr_aliasing 2.000s 54.949us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
aes_csr_mem_rw_with_rand_reset 2.000s 98.553us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
aes_csr_rw 1.000s 60.003us 1 1 100.00
aes_csr_aliasing 2.000s 54.949us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
algorithm 3 3 100.00
aes_smoke 2.000s 85.643us 1 1 100.00
aes_config_error 2.000s 116.387us 1 1 100.00
aes_stress 4.000s 120.736us 1 1 100.00
key_length 3 3 100.00
aes_smoke 2.000s 85.643us 1 1 100.00
aes_config_error 2.000s 116.387us 1 1 100.00
aes_stress 4.000s 120.736us 1 1 100.00
back2back 2 2 100.00
aes_stress 4.000s 120.736us 1 1 100.00
aes_b2b 5.000s 186.432us 1 1 100.00
backpressure 1 1 100.00
aes_stress 4.000s 120.736us 1 1 100.00
multi_message 4 4 100.00
aes_smoke 2.000s 85.643us 1 1 100.00
aes_config_error 2.000s 116.387us 1 1 100.00
aes_stress 4.000s 120.736us 1 1 100.00
aes_alert_reset 4.000s 187.490us 1 1 100.00
failure_test 3 3 100.00
aes_man_cfg_err 2.000s 119.077us 1 1 100.00
aes_config_error 2.000s 116.387us 1 1 100.00
aes_alert_reset 4.000s 187.490us 1 1 100.00
trigger_clear_test 1 1 100.00
aes_clear 3.000s 151.053us 1 1 100.00
nist_test_vectors 1 1 100.00
aes_nist_vectors 5.000s 133.061us 1 1 100.00
reset_recovery 1 1 100.00
aes_alert_reset 4.000s 187.490us 1 1 100.00
stress 1 1 100.00
aes_stress 4.000s 120.736us 1 1 100.00
sideload 2 2 100.00
aes_stress 4.000s 120.736us 1 1 100.00
aes_sideload 2.000s 66.819us 1 1 100.00
deinitialization 1 1 100.00
aes_deinit 3.000s 75.187us 1 1 100.00
stress_all 0 1 0.00
aes_stress_all 8.000s 440.125us 0 1 0.00
alert_test 1 1 100.00
aes_alert_test 3.000s 93.803us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
aes_tl_errors 4.000s 90.683us 1 1 100.00
tl_d_illegal_access 1 1 100.00
aes_tl_errors 4.000s 90.683us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
aes_csr_hw_reset 1.000s 106.401us 1 1 100.00
aes_csr_rw 1.000s 60.003us 1 1 100.00
aes_csr_aliasing 2.000s 54.949us 1 1 100.00
aes_same_csr_outstanding 2.000s 121.574us 1 1 100.00
tl_d_partial_access 4 4 100.00
aes_csr_hw_reset 1.000s 106.401us 1 1 100.00
aes_csr_rw 1.000s 60.003us 1 1 100.00
aes_csr_aliasing 2.000s 54.949us 1 1 100.00
aes_same_csr_outstanding 2.000s 121.574us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
reseeding 1 1 100.00
aes_reseed 2.000s 78.768us 1 1 100.00
fault_inject 2 3 66.67
aes_fi 3.000s 98.807us 0 1 0.00
aes_control_fi 2.000s 47.084us 1 1 100.00
aes_cipher_fi 2.000s 48.243us 1 1 100.00
shadow_reg_update_error 1 1 100.00
aes_shadow_reg_errors 2.000s 177.938us 1 1 100.00
shadow_reg_read_clear_staged_value 1 1 100.00
aes_shadow_reg_errors 2.000s 177.938us 1 1 100.00
shadow_reg_storage_error 1 1 100.00
aes_shadow_reg_errors 2.000s 177.938us 1 1 100.00
shadowed_reset_glitch 1 1 100.00
aes_shadow_reg_errors 2.000s 177.938us 1 1 100.00
shadow_reg_update_error_with_csr_rw 1 1 100.00
aes_shadow_reg_errors_with_csr_rw 3.000s 432.570us 1 1 100.00
tl_intg_err 2 2 100.00
aes_sec_cm 4.000s 470.526us 1 1 100.00
aes_tl_intg_err 3.000s 129.613us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
aes_tl_intg_err 3.000s 129.613us 1 1 100.00
sec_cm_lc_escalate_en_intersig_mubi 1 1 100.00
aes_alert_reset 4.000s 187.490us 1 1 100.00
sec_cm_main_config_shadow 1 1 100.00
aes_shadow_reg_errors 2.000s 177.938us 1 1 100.00
sec_cm_gcm_config_shadow 1 1 100.00
aes_shadow_reg_errors 2.000s 177.938us 1 1 100.00
sec_cm_main_config_sparse 4 4 100.00
aes_smoke 2.000s 85.643us 1 1 100.00
aes_stress 4.000s 120.736us 1 1 100.00
aes_alert_reset 4.000s 187.490us 1 1 100.00
aes_core_fi 2.000s 290.961us 1 1 100.00
sec_cm_gcm_config_sparse 3 3 100.00
aes_config_error 2.000s 116.387us 1 1 100.00
aes_stress 4.000s 120.736us 1 1 100.00
aes_core_fi 2.000s 290.961us 1 1 100.00
sec_cm_aux_config_shadow 1 1 100.00
aes_shadow_reg_errors 2.000s 177.938us 1 1 100.00
sec_cm_aux_config_regwen 2 2 100.00
aes_readability 2.000s 81.530us 1 1 100.00
aes_stress 4.000s 120.736us 1 1 100.00
sec_cm_key_sideload 2 2 100.00
aes_stress 4.000s 120.736us 1 1 100.00
aes_sideload 2.000s 66.819us 1 1 100.00
sec_cm_key_sw_unreadable 1 1 100.00
aes_readability 2.000s 81.530us 1 1 100.00
sec_cm_data_reg_sw_unreadable 1 1 100.00
aes_readability 2.000s 81.530us 1 1 100.00
sec_cm_key_sec_wipe 1 1 100.00
aes_readability 2.000s 81.530us 1 1 100.00
sec_cm_iv_config_sec_wipe 1 1 100.00
aes_readability 2.000s 81.530us 1 1 100.00
sec_cm_data_reg_sec_wipe 1 1 100.00
aes_readability 2.000s 81.530us 1 1 100.00
sec_cm_data_reg_key_sca 1 1 100.00
aes_stress 4.000s 120.736us 1 1 100.00
sec_cm_key_masking 1 1 100.00
aes_stress 4.000s 120.736us 1 1 100.00
sec_cm_main_fsm_sparse 0 1 0.00
aes_fi 3.000s 98.807us 0 1 0.00
sec_cm_main_fsm_redun 3 4 75.00
aes_fi 3.000s 98.807us 0 1 0.00
aes_control_fi 2.000s 47.084us 1 1 100.00
aes_cipher_fi 2.000s 48.243us 1 1 100.00
aes_ctr_fi 2.000s 52.032us 1 1 100.00
sec_cm_cipher_fsm_sparse 0 1 0.00
aes_fi 3.000s 98.807us 0 1 0.00
sec_cm_cipher_fsm_redun 2 3 66.67
aes_fi 3.000s 98.807us 0 1 0.00
aes_control_fi 2.000s 47.084us 1 1 100.00
aes_cipher_fi 2.000s 48.243us 1 1 100.00
sec_cm_cipher_ctr_redun 1 1 100.00
aes_cipher_fi 2.000s 48.243us 1 1 100.00
sec_cm_ctr_fsm_sparse 0 1 0.00
aes_fi 3.000s 98.807us 0 1 0.00
sec_cm_ctr_fsm_redun 2 3 66.67
aes_fi 3.000s 98.807us 0 1 0.00
aes_control_fi 2.000s 47.084us 1 1 100.00
aes_ctr_fi 2.000s 52.032us 1 1 100.00
sec_cm_ghash_fsm_sparse 0 1 0.00
aes_fi 3.000s 98.807us 0 1 0.00
sec_cm_ctrl_sparse 3 4 75.00
aes_fi 3.000s 98.807us 0 1 0.00
aes_control_fi 2.000s 47.084us 1 1 100.00
aes_cipher_fi 2.000s 48.243us 1 1 100.00
aes_ctr_fi 2.000s 52.032us 1 1 100.00
sec_cm_main_fsm_global_esc 1 1 100.00
aes_alert_reset 4.000s 187.490us 1 1 100.00
sec_cm_main_fsm_local_esc 3 4 75.00
aes_fi 3.000s 98.807us 0 1 0.00
aes_control_fi 2.000s 47.084us 1 1 100.00
aes_cipher_fi 2.000s 48.243us 1 1 100.00
aes_ctr_fi 2.000s 52.032us 1 1 100.00
sec_cm_cipher_fsm_local_esc 3 4 75.00
aes_fi 3.000s 98.807us 0 1 0.00
aes_control_fi 2.000s 47.084us 1 1 100.00
aes_cipher_fi 2.000s 48.243us 1 1 100.00
aes_ctr_fi 2.000s 52.032us 1 1 100.00
sec_cm_ctr_fsm_local_esc 2 3 66.67
aes_fi 3.000s 98.807us 0 1 0.00
aes_control_fi 2.000s 47.084us 1 1 100.00
aes_ctr_fi 2.000s 52.032us 1 1 100.00
sec_cm_ghash_fsm_local_esc 0 1 0.00
aes_fi 3.000s 98.807us 0 1 0.00
sec_cm_data_reg_local_esc 2 3 66.67
aes_fi 3.000s 98.807us 0 1 0.00
aes_control_fi 2.000s 47.084us 1 1 100.00
aes_cipher_fi 2.000s 48.243us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 0 1 0.00
aes_stress_all_with_rand_reset 18.000s 3574.645us 0 1 0.00

Error Messages

   Test seed line log context
UVM_FATAL (aes_scoreboard.sv:923) scoreboard [scoreboard] 1 test run
aes_fi 52756591064696434118173361402684881207922879788223674543070174265686192335685 4940
----| NO FAILURES BUT NUMBER OF EXPECTED MESSAGES DOES NOT MATCH ACTUAL
----| Expected: 3
----| Seen: 2
----| Expected corrupted: 0
UVM_ERROR (uvm_sequencer_base.svh:757) sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'sequencer' for sequence 'parent_sequence' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues 1 test run
aes_stress_all 85760359423810942243870826915707909612232005095861727193142765247460727365568 13159
UVM_INFO @ 440124835 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (cip_base_vseq.sv:1230) [aes_common_vseq] Check failed (vseq_done) 1 test run
aes_stress_all_with_rand_reset 88821679793169754016950964330347849405555333647404843388637069692765961813510 547
UVM_INFO @ 3574644811 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---