Simulation Results: alert_handler

 
01/09/2026 21:34:42 DVSim: v1.52.0 sha: 4e5c99d json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 86.58 %
  • code
  • 87.73 %
  • assert
  • 97.75 %
  • func
  • 74.27 %
  • line
  • 99.61 %
  • branch
  • 97.84 %
  • cond
  • 90.56 %
  • toggle
  • 86.14 %
  • FSM
  • 64.52 %
Validation stages
V1
100.00%
V2
89.47%
V2S
100.00%
V3
0.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
alert_handler_smoke 12.870s 714.328us 1 1 100.00
csr_hw_reset 1 1 100.00
alert_handler_csr_hw_reset 4.760s 232.255us 1 1 100.00
csr_rw 1 1 100.00
alert_handler_csr_rw 5.660s 63.896us 1 1 100.00
csr_bit_bash 1 1 100.00
alert_handler_csr_bit_bash 271.580s 2890.535us 1 1 100.00
csr_aliasing 1 1 100.00
alert_handler_csr_aliasing 31.500s 264.536us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
alert_handler_csr_mem_rw_with_rand_reset 11.070s 239.542us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
alert_handler_csr_rw 5.660s 63.896us 1 1 100.00
alert_handler_csr_aliasing 31.500s 264.536us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
esc_accum 1 1 100.00
alert_handler_esc_alert_accum 202.850s 13426.109us 1 1 100.00
esc_timeout 1 1 100.00
alert_handler_esc_intr_timeout 8.900s 222.061us 1 1 100.00
entropy 1 1 100.00
alert_handler_entropy 2693.610s 48995.436us 1 1 100.00
sig_int_fail 1 1 100.00
alert_handler_sig_int_fail 3.160s 139.310us 1 1 100.00
clk_skew 1 1 100.00
alert_handler_smoke 12.870s 714.328us 1 1 100.00
random_alerts 1 1 100.00
alert_handler_random_alerts 39.980s 786.199us 1 1 100.00
random_classes 1 1 100.00
alert_handler_random_classes 9.740s 638.895us 1 1 100.00
ping_timeout 1 1 100.00
alert_handler_ping_timeout 274.070s 24990.994us 1 1 100.00
lpg 2 2 100.00
alert_handler_lpg 1198.320s 59367.137us 1 1 100.00
alert_handler_lpg_stub_clk 2244.180s 41923.636us 1 1 100.00
stress_all 0 1 0.00
alert_handler_stress_all 4167.530s 108777.387us 0 1 0.00
alert_handler_entropy_stress_test 0 1 0.00
alert_handler_entropy_stress 7.490s 130.150us 0 1 0.00
alert_handler_alert_accum_saturation 1 1 100.00
alert_handler_alert_accum_saturation 2.810s 31.257us 1 1 100.00
intr_test 1 1 100.00
alert_handler_intr_test 2.220s 10.166us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
alert_handler_tl_errors 7.280s 78.353us 1 1 100.00
tl_d_illegal_access 1 1 100.00
alert_handler_tl_errors 7.280s 78.353us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
alert_handler_csr_hw_reset 4.760s 232.255us 1 1 100.00
alert_handler_csr_rw 5.660s 63.896us 1 1 100.00
alert_handler_csr_aliasing 31.500s 264.536us 1 1 100.00
alert_handler_same_csr_outstanding 55.570s 1443.659us 1 1 100.00
tl_d_partial_access 4 4 100.00
alert_handler_csr_hw_reset 4.760s 232.255us 1 1 100.00
alert_handler_csr_rw 5.660s 63.896us 1 1 100.00
alert_handler_csr_aliasing 31.500s 264.536us 1 1 100.00
alert_handler_same_csr_outstanding 55.570s 1443.659us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
shadow_reg_update_error 1 1 100.00
alert_handler_shadow_reg_errors 172.040s 21770.181us 1 1 100.00
shadow_reg_read_clear_staged_value 1 1 100.00
alert_handler_shadow_reg_errors 172.040s 21770.181us 1 1 100.00
shadow_reg_storage_error 1 1 100.00
alert_handler_shadow_reg_errors 172.040s 21770.181us 1 1 100.00
shadowed_reset_glitch 1 1 100.00
alert_handler_shadow_reg_errors 172.040s 21770.181us 1 1 100.00
shadow_reg_update_error_with_csr_rw 1 1 100.00
alert_handler_shadow_reg_errors_with_csr_rw 348.280s 5010.082us 1 1 100.00
tl_intg_err 2 2 100.00
alert_handler_sec_cm 25.730s 2223.101us 1 1 100.00
alert_handler_tl_intg_err 10.980s 333.231us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
alert_handler_tl_intg_err 10.980s 333.231us 1 1 100.00
sec_cm_config_shadow 1 1 100.00
alert_handler_shadow_reg_errors 172.040s 21770.181us 1 1 100.00
sec_cm_ping_timer_config_regwen 1 1 100.00
alert_handler_smoke 12.870s 714.328us 1 1 100.00
sec_cm_alert_config_regwen 1 1 100.00
alert_handler_smoke 12.870s 714.328us 1 1 100.00
sec_cm_alert_loc_config_regwen 1 1 100.00
alert_handler_smoke 12.870s 714.328us 1 1 100.00
sec_cm_class_config_regwen 1 1 100.00
alert_handler_smoke 12.870s 714.328us 1 1 100.00
sec_cm_alert_intersig_diff 1 1 100.00
alert_handler_sig_int_fail 3.160s 139.310us 1 1 100.00
sec_cm_lpg_intersig_mubi 1 1 100.00
alert_handler_lpg 1198.320s 59367.137us 1 1 100.00
sec_cm_esc_intersig_diff 1 1 100.00
alert_handler_sig_int_fail 3.160s 139.310us 1 1 100.00
sec_cm_alert_rx_intersig_bkgn_chk 1 1 100.00
alert_handler_entropy 2693.610s 48995.436us 1 1 100.00
sec_cm_esc_tx_intersig_bkgn_chk 1 1 100.00
alert_handler_entropy 2693.610s 48995.436us 1 1 100.00
sec_cm_esc_timer_fsm_sparse 1 1 100.00
alert_handler_sec_cm 25.730s 2223.101us 1 1 100.00
sec_cm_ping_timer_fsm_sparse 1 1 100.00
alert_handler_sec_cm 25.730s 2223.101us 1 1 100.00
sec_cm_esc_timer_fsm_local_esc 1 1 100.00
alert_handler_sec_cm 25.730s 2223.101us 1 1 100.00
sec_cm_ping_timer_fsm_local_esc 1 1 100.00
alert_handler_sec_cm 25.730s 2223.101us 1 1 100.00
sec_cm_esc_timer_fsm_global_esc 1 1 100.00
alert_handler_sec_cm 25.730s 2223.101us 1 1 100.00
sec_cm_accu_ctr_redun 1 1 100.00
alert_handler_sec_cm 25.730s 2223.101us 1 1 100.00
sec_cm_esc_timer_ctr_redun 1 1 100.00
alert_handler_sec_cm 25.730s 2223.101us 1 1 100.00
sec_cm_ping_timer_ctr_redun 1 1 100.00
alert_handler_sec_cm 25.730s 2223.101us 1 1 100.00
sec_cm_ping_timer_lfsr_redun 1 1 100.00
alert_handler_sec_cm 25.730s 2223.101us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 0 1 0.00
alert_handler_stress_all_with_rand_reset 370.270s 3347.787us 0 1 0.00

Error Messages

   Test seed line log context
UVM_ERROR sequencer [alert_sender_ping_rsp_seq] Response queue overflow, response was dropped 1 test run
alert_handler_entropy_stress 57266730908493635427056718607220436060896143510257151162993169000788114806926 212
UVM_INFO @ 130149560 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (alert_handler_scoreboard.sv:258) scoreboard [scoreboard] Unexpected interrupt value in cfg.intr_vif.pins[*]: saw *, but expected *. (is_int_err = *, local_alert_type = LocalEscIntFail) 1 test run
alert_handler_stress_all 19876585540203389599902162826553172921240614995354985992670836599291083409432 360
UVM_INFO @ 108777386831 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (cip_base_vseq.sv:1296) [alert_handler_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. 1 test run
alert_handler_stress_all_with_rand_reset 43086494001737592516580575621189653761310517551438929880079726830660345578133 221
UVM_INFO @ 3347786798 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---