Simulation Results: dma

 
01/09/2026 21:34:42 DVSim: v1.52.0 sha: 4e5c99d json Branch: master Tool: xcelium [24.03-s007]
Coverage statistics
  • Total
  • 83.32 %
  • code
  • 90.38 %
  • assert
  • 95.87 %
  • func
  • 63.71 %
  • block
  • 97.34 %
  • line
  • 96.85 %
  • branch
  • 95.76 %
  • toggle
  • 77.37 %
  • FSM
  • 91.55 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
unmapped
66.67%
Testpoint Test Max Runtime Sim Time Pass Total %
dma_memory_smoke 1 1 100.00
dma_memory_smoke 7.000s 1099.575us 1 1 100.00
dma_handshake_smoke 1 1 100.00
dma_handshake_smoke 5.000s 286.537us 1 1 100.00
dma_generic_smoke 1 1 100.00
dma_generic_smoke 5.000s 1014.772us 1 1 100.00
csr_hw_reset 1 1 100.00
dma_csr_hw_reset 2.000s 31.415us 1 1 100.00
csr_rw 1 1 100.00
dma_csr_rw 1.000s 18.371us 1 1 100.00
csr_bit_bash 1 1 100.00
dma_csr_bit_bash 9.000s 8059.656us 1 1 100.00
csr_aliasing 1 1 100.00
dma_csr_aliasing 2.000s 31.735us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
dma_csr_mem_rw_with_rand_reset 2.000s 21.439us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
dma_csr_rw 1.000s 18.371us 1 1 100.00
dma_csr_aliasing 2.000s 31.735us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
dma_memory_region_lock 1 1 100.00
dma_memory_region_lock 83.000s 3720.067us 1 1 100.00
dma_memory_tl_error 1 1 100.00
dma_memory_stress 755.000s 204838.853us 1 1 100.00
dma_handshake_tl_error 1 1 100.00
dma_handshake_stress 322.000s 23708.770us 1 1 100.00
dma_handshake_stress 1 1 100.00
dma_handshake_stress 322.000s 23708.770us 1 1 100.00
dma_memory_stress 1 1 100.00
dma_memory_stress 755.000s 204838.853us 1 1 100.00
dma_generic_stress 1 1 100.00
dma_generic_stress 245.000s 14718.522us 1 1 100.00
dma_handshake_mem_buffer_overflow 1 1 100.00
dma_handshake_stress 322.000s 23708.770us 1 1 100.00
dma_abort 1 1 100.00
dma_abort 9.000s 499.880us 1 1 100.00
dma_stress_all 1 1 100.00
dma_stress_all 138.000s 17081.643us 1 1 100.00
alert_test 1 1 100.00
dma_alert_test 1.000s 20.272us 1 1 100.00
intr_test 1 1 100.00
dma_intr_test 1.000s 36.321us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
dma_tl_errors 2.000s 94.001us 1 1 100.00
tl_d_illegal_access 1 1 100.00
dma_tl_errors 2.000s 94.001us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
dma_csr_hw_reset 2.000s 31.415us 1 1 100.00
dma_csr_rw 1.000s 18.371us 1 1 100.00
dma_csr_aliasing 2.000s 31.735us 1 1 100.00
dma_same_csr_outstanding 2.000s 1990.578us 1 1 100.00
tl_d_partial_access 4 4 100.00
dma_csr_hw_reset 2.000s 31.415us 1 1 100.00
dma_csr_rw 1.000s 18.371us 1 1 100.00
dma_csr_aliasing 2.000s 31.735us 1 1 100.00
dma_same_csr_outstanding 2.000s 1990.578us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
dma_illegal_addr_range 3 3 100.00
dma_mem_enabled 13.000s 231.016us 1 1 100.00
dma_generic_stress 245.000s 14718.522us 1 1 100.00
dma_handshake_stress 322.000s 23708.770us 1 1 100.00
dma_config_lock 1 1 100.00
dma_config_lock 7.000s 329.439us 1 1 100.00
tl_intg_err 2 2 100.00
dma_tl_intg_err 2.000s 98.243us 1 1 100.00
dma_sec_cm 1.000s 13.080us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
Unmapped 2 3 66.67
dma_short_transfer 193.000s 15596.145us 1 1 100.00
dma_longer_transfer 8.000s 653.022us 1 1 100.00
dma_stress_all_with_rand_reset 3.000s 427.633us 0 1 0.00

Error Messages

   Test seed line log context
UVM_ERROR @ *ps: (cip_base_vseq.sv:1297) [dma_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. 1 test run
dma_stress_all_with_rand_reset 94553738047984215306138100091094936860927390038940046316597635897312675292026 91
UVM_INFO @ 427633013ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---