Simulation Results: edn/edn0

 
01/09/2026 21:34:42 DVSim: v1.52.0 sha: 4e5c99d json Branch: master Tool: xcelium [24.03-s007]
Coverage statistics
  • Total
  • 76.02 %
  • code
  • 84.61 %
  • assert
  • 94.91 %
  • func
  • 48.53 %
  • block
  • 94.38 %
  • line
  • 97.12 %
  • branch
  • 87.91 %
  • toggle
  • 69.70 %
  • FSM
  • 83.72 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
V3
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
edn_smoke 2.000s 48.833us 1 1 100.00
csr_hw_reset 1 1 100.00
edn_csr_hw_reset 1.000s 48.869us 1 1 100.00
csr_rw 1 1 100.00
edn_csr_rw 2.000s 82.083us 1 1 100.00
csr_bit_bash 1 1 100.00
edn_csr_bit_bash 4.000s 617.514us 1 1 100.00
csr_aliasing 1 1 100.00
edn_csr_aliasing 1.000s 30.633us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
edn_csr_mem_rw_with_rand_reset 2.000s 144.624us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
edn_csr_rw 2.000s 82.083us 1 1 100.00
edn_csr_aliasing 1.000s 30.633us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
firmware 1 1 100.00
edn_genbits 2.000s 54.441us 1 1 100.00
csrng_commands 1 1 100.00
edn_genbits 2.000s 54.441us 1 1 100.00
genbits 1 1 100.00
edn_genbits 2.000s 54.441us 1 1 100.00
interrupts 1 1 100.00
edn_intr 2.000s 23.462us 1 1 100.00
alerts 1 1 100.00
edn_alert 2.000s 26.692us 1 1 100.00
errs 1 1 100.00
edn_err 2.000s 25.356us 1 1 100.00
disable 2 2 100.00
edn_disable 2.000s 12.149us 1 1 100.00
edn_disable_auto_req_mode 2.000s 36.325us 1 1 100.00
stress_all 1 1 100.00
edn_stress_all 11.000s 240.459us 1 1 100.00
intr_test 1 1 100.00
edn_intr_test 1.000s 55.956us 1 1 100.00
alert_test 1 1 100.00
edn_alert_test 1.000s 51.032us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
edn_tl_errors 2.000s 90.741us 1 1 100.00
tl_d_illegal_access 1 1 100.00
edn_tl_errors 2.000s 90.741us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
edn_csr_hw_reset 1.000s 48.869us 1 1 100.00
edn_csr_rw 2.000s 82.083us 1 1 100.00
edn_csr_aliasing 1.000s 30.633us 1 1 100.00
edn_same_csr_outstanding 2.000s 17.659us 1 1 100.00
tl_d_partial_access 4 4 100.00
edn_csr_hw_reset 1.000s 48.869us 1 1 100.00
edn_csr_rw 2.000s 82.083us 1 1 100.00
edn_csr_aliasing 1.000s 30.633us 1 1 100.00
edn_same_csr_outstanding 2.000s 17.659us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
edn_sec_cm 9.000s 2339.465us 1 1 100.00
edn_tl_intg_err 2.000s 489.422us 1 1 100.00
sec_cm_config_regwen 1 1 100.00
edn_regwen 2.000s 182.259us 1 1 100.00
sec_cm_config_mubi 1 1 100.00
edn_alert 2.000s 26.692us 1 1 100.00
sec_cm_main_sm_fsm_sparse 1 1 100.00
edn_sec_cm 9.000s 2339.465us 1 1 100.00
sec_cm_ack_sm_fsm_sparse 1 1 100.00
edn_sec_cm 9.000s 2339.465us 1 1 100.00
sec_cm_fifo_ctr_redun 1 1 100.00
edn_sec_cm 9.000s 2339.465us 1 1 100.00
sec_cm_ctr_redun 1 1 100.00
edn_sec_cm 9.000s 2339.465us 1 1 100.00
sec_cm_main_sm_ctr_local_esc 2 2 100.00
edn_alert 2.000s 26.692us 1 1 100.00
edn_sec_cm 9.000s 2339.465us 1 1 100.00
sec_cm_cs_rdata_bus_consistency 1 1 100.00
edn_alert 2.000s 26.692us 1 1 100.00
sec_cm_tile_link_bus_integrity 1 1 100.00
edn_tl_intg_err 2.000s 489.422us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 1 1 100.00
edn_stress_all_with_rand_reset 29.000s 2826.349us 1 1 100.00