Simulation Results: edn/edn1

 
01/09/2026 21:34:42 DVSim: v1.52.0 sha: 4e5c99d json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 86.46 %
  • code
  • 81.98 %
  • assert
  • 97.14 %
  • func
  • 80.25 %
  • line
  • 98.18 %
  • branch
  • 93.51 %
  • cond
  • 90.85 %
  • toggle
  • 86.46 %
  • FSM
  • 40.91 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
V3
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
edn_smoke 1.090s 44.737us 1 1 100.00
csr_hw_reset 1 1 100.00
edn_csr_hw_reset 0.980s 36.121us 1 1 100.00
csr_rw 1 1 100.00
edn_csr_rw 1.030s 33.667us 1 1 100.00
csr_bit_bash 1 1 100.00
edn_csr_bit_bash 3.280s 163.589us 1 1 100.00
csr_aliasing 1 1 100.00
edn_csr_aliasing 0.880s 19.090us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
edn_csr_mem_rw_with_rand_reset 1.350s 89.164us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
edn_csr_rw 1.030s 33.667us 1 1 100.00
edn_csr_aliasing 0.880s 19.090us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
firmware 1 1 100.00
edn_genbits 1.430s 92.025us 1 1 100.00
csrng_commands 1 1 100.00
edn_genbits 1.430s 92.025us 1 1 100.00
genbits 1 1 100.00
edn_genbits 1.430s 92.025us 1 1 100.00
interrupts 1 1 100.00
edn_intr 1.240s 20.516us 1 1 100.00
alerts 1 1 100.00
edn_alert 1.130s 30.171us 1 1 100.00
errs 1 1 100.00
edn_err 1.100s 43.154us 1 1 100.00
disable 2 2 100.00
edn_disable 0.870s 10.900us 1 1 100.00
edn_disable_auto_req_mode 1.330s 107.877us 1 1 100.00
stress_all 1 1 100.00
edn_stress_all 5.640s 383.600us 1 1 100.00
intr_test 1 1 100.00
edn_intr_test 0.970s 81.056us 1 1 100.00
alert_test 1 1 100.00
edn_alert_test 1.060s 36.656us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
edn_tl_errors 1.900s 153.460us 1 1 100.00
tl_d_illegal_access 1 1 100.00
edn_tl_errors 1.900s 153.460us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
edn_csr_hw_reset 0.980s 36.121us 1 1 100.00
edn_csr_rw 1.030s 33.667us 1 1 100.00
edn_csr_aliasing 0.880s 19.090us 1 1 100.00
edn_same_csr_outstanding 1.000s 48.601us 1 1 100.00
tl_d_partial_access 4 4 100.00
edn_csr_hw_reset 0.980s 36.121us 1 1 100.00
edn_csr_rw 1.030s 33.667us 1 1 100.00
edn_csr_aliasing 0.880s 19.090us 1 1 100.00
edn_same_csr_outstanding 1.000s 48.601us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
edn_sec_cm 2.510s 670.529us 1 1 100.00
edn_tl_intg_err 1.880s 182.111us 1 1 100.00
sec_cm_config_regwen 1 1 100.00
edn_regwen 1.250s 16.980us 1 1 100.00
sec_cm_config_mubi 1 1 100.00
edn_alert 1.130s 30.171us 1 1 100.00
sec_cm_main_sm_fsm_sparse 1 1 100.00
edn_sec_cm 2.510s 670.529us 1 1 100.00
sec_cm_ack_sm_fsm_sparse 1 1 100.00
edn_sec_cm 2.510s 670.529us 1 1 100.00
sec_cm_fifo_ctr_redun 1 1 100.00
edn_sec_cm 2.510s 670.529us 1 1 100.00
sec_cm_ctr_redun 1 1 100.00
edn_sec_cm 2.510s 670.529us 1 1 100.00
sec_cm_main_sm_ctr_local_esc 2 2 100.00
edn_alert 1.130s 30.171us 1 1 100.00
edn_sec_cm 2.510s 670.529us 1 1 100.00
sec_cm_cs_rdata_bus_consistency 1 1 100.00
edn_alert 1.130s 30.171us 1 1 100.00
sec_cm_tile_link_bus_integrity 1 1 100.00
edn_tl_intg_err 1.880s 182.111us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 1 1 100.00
edn_stress_all_with_rand_reset 94.670s 3753.502us 1 1 100.00