| V1 |
|
100.00% |
| V2 |
|
93.75% |
| V2S |
|
85.71% |
| V3 |
|
50.00% |
| Testpoint | Test | Max Runtime | Sim Time | Pass | Total | % |
|---|---|---|---|---|---|---|
| smoke | 1 | 1 | 100.00 | |||
| entropy_src_smoke | 3.000s | 25.087us | 1 | 1 | 100.00 | |
| csr_hw_reset | 1 | 1 | 100.00 | |||
| entropy_src_csr_hw_reset | 2.000s | 90.836us | 1 | 1 | 100.00 | |
| csr_rw | 1 | 1 | 100.00 | |||
| entropy_src_csr_rw | 2.000s | 138.881us | 1 | 1 | 100.00 | |
| csr_bit_bash | 1 | 1 | 100.00 | |||
| entropy_src_csr_bit_bash | 28.000s | 3646.445us | 1 | 1 | 100.00 | |
| csr_aliasing | 1 | 1 | 100.00 | |||
| entropy_src_csr_aliasing | 2.000s | 46.210us | 1 | 1 | 100.00 | |
| csr_mem_rw_with_rand_reset | 1 | 1 | 100.00 | |||
| entropy_src_csr_mem_rw_with_rand_reset | 3.000s | 42.100us | 1 | 1 | 100.00 | |
| regwen_csr_and_corresponding_lockable_csr | 2 | 2 | 100.00 | |||
| entropy_src_csr_rw | 2.000s | 138.881us | 1 | 1 | 100.00 | |
| entropy_src_csr_aliasing | 2.000s | 46.210us | 1 | 1 | 100.00 | |
| Testpoint | Test | Max Runtime | Sim Time | Pass | Total | % |
|---|---|---|---|---|---|---|
| firmware | 2 | 3 | 66.67 | |||
| entropy_src_smoke | 3.000s | 25.087us | 1 | 1 | 100.00 | |
| entropy_src_rng | 118.000s | 14316.693us | 1 | 1 | 100.00 | |
| entropy_src_fw_ov | 3600.000s | 0.000us | 0 | 1 | 0.00 | |
| firmware_mode | 0 | 1 | 0.00 | |||
| entropy_src_fw_ov | 3600.000s | 0.000us | 0 | 1 | 0.00 | |
| rng_mode | 1 | 1 | 100.00 | |||
| entropy_src_rng | 118.000s | 14316.693us | 1 | 1 | 100.00 | |
| rng_max_rate | 1 | 1 | 100.00 | |||
| entropy_src_rng_max_rate | 668.000s | 14046.764us | 1 | 1 | 100.00 | |
| health_checks | 1 | 1 | 100.00 | |||
| entropy_src_rng | 118.000s | 14316.693us | 1 | 1 | 100.00 | |
| conditioning | 1 | 1 | 100.00 | |||
| entropy_src_rng | 118.000s | 14316.693us | 1 | 1 | 100.00 | |
| interrupts | 2 | 2 | 100.00 | |||
| entropy_src_rng | 118.000s | 14316.693us | 1 | 1 | 100.00 | |
| entropy_src_intr | 20.000s | 1934.275us | 1 | 1 | 100.00 | |
| alerts | 2 | 2 | 100.00 | |||
| entropy_src_rng | 118.000s | 14316.693us | 1 | 1 | 100.00 | |
| entropy_src_functional_alerts | 9.000s | 679.873us | 1 | 1 | 100.00 | |
| stress_all | 1 | 1 | 100.00 | |||
| entropy_src_stress_all | 251.000s | 14239.544us | 1 | 1 | 100.00 | |
| functional_errors | 1 | 1 | 100.00 | |||
| entropy_src_functional_errors | 3.000s | 30.604us | 1 | 1 | 100.00 | |
| firmware_ov_read_contiguous_data | 1 | 1 | 100.00 | |||
| entropy_src_fw_ov_contiguous | 4.000s | 123.188us | 1 | 1 | 100.00 | |
| intr_test | 1 | 1 | 100.00 | |||
| entropy_src_intr_test | 2.000s | 19.764us | 1 | 1 | 100.00 | |
| alert_test | 1 | 1 | 100.00 | |||
| entropy_src_alert_test | 2.000s | 60.592us | 1 | 1 | 100.00 | |
| tl_d_oob_addr_access | 1 | 1 | 100.00 | |||
| entropy_src_tl_errors | 4.000s | 174.076us | 1 | 1 | 100.00 | |
| tl_d_illegal_access | 1 | 1 | 100.00 | |||
| entropy_src_tl_errors | 4.000s | 174.076us | 1 | 1 | 100.00 | |
| tl_d_outstanding_access | 4 | 4 | 100.00 | |||
| entropy_src_csr_hw_reset | 2.000s | 90.836us | 1 | 1 | 100.00 | |
| entropy_src_csr_rw | 2.000s | 138.881us | 1 | 1 | 100.00 | |
| entropy_src_csr_aliasing | 2.000s | 46.210us | 1 | 1 | 100.00 | |
| entropy_src_same_csr_outstanding | 3.000s | 690.369us | 1 | 1 | 100.00 | |
| tl_d_partial_access | 4 | 4 | 100.00 | |||
| entropy_src_csr_hw_reset | 2.000s | 90.836us | 1 | 1 | 100.00 | |
| entropy_src_csr_rw | 2.000s | 138.881us | 1 | 1 | 100.00 | |
| entropy_src_csr_aliasing | 2.000s | 46.210us | 1 | 1 | 100.00 | |
| entropy_src_same_csr_outstanding | 3.000s | 690.369us | 1 | 1 | 100.00 | |
| Testpoint | Test | Max Runtime | Sim Time | Pass | Total | % |
|---|---|---|---|---|---|---|
| tl_intg_err | 2 | 2 | 100.00 | |||
| entropy_src_sec_cm | 3.000s | 104.054us | 1 | 1 | 100.00 | |
| entropy_src_tl_intg_err | 5.000s | 284.652us | 1 | 1 | 100.00 | |
| sec_cm_config_regwen | 2 | 2 | 100.00 | |||
| entropy_src_rng | 118.000s | 14316.693us | 1 | 1 | 100.00 | |
| entropy_src_cfg_regwen | 2.000s | 61.436us | 1 | 1 | 100.00 | |
| sec_cm_config_mubi | 1 | 1 | 100.00 | |||
| entropy_src_rng | 118.000s | 14316.693us | 1 | 1 | 100.00 | |
| sec_cm_config_redun | 1 | 1 | 100.00 | |||
| entropy_src_rng | 118.000s | 14316.693us | 1 | 1 | 100.00 | |
| sec_cm_intersig_mubi | 1 | 2 | 50.00 | |||
| entropy_src_rng | 118.000s | 14316.693us | 1 | 1 | 100.00 | |
| entropy_src_fw_ov | 3600.000s | 0.000us | 0 | 1 | 0.00 | |
| sec_cm_main_sm_fsm_sparse | 2 | 2 | 100.00 | |||
| entropy_src_functional_errors | 3.000s | 30.604us | 1 | 1 | 100.00 | |
| entropy_src_sec_cm | 3.000s | 104.054us | 1 | 1 | 100.00 | |
| sec_cm_ack_sm_fsm_sparse | 2 | 2 | 100.00 | |||
| entropy_src_functional_errors | 3.000s | 30.604us | 1 | 1 | 100.00 | |
| entropy_src_sec_cm | 3.000s | 104.054us | 1 | 1 | 100.00 | |
| sec_cm_rng_bkgn_chk | 1 | 1 | 100.00 | |||
| entropy_src_rng | 118.000s | 14316.693us | 1 | 1 | 100.00 | |
| sec_cm_fifo_ctr_redun | 2 | 2 | 100.00 | |||
| entropy_src_functional_errors | 3.000s | 30.604us | 1 | 1 | 100.00 | |
| entropy_src_sec_cm | 3.000s | 104.054us | 1 | 1 | 100.00 | |
| sec_cm_ctr_redun | 2 | 2 | 100.00 | |||
| entropy_src_functional_errors | 3.000s | 30.604us | 1 | 1 | 100.00 | |
| entropy_src_sec_cm | 3.000s | 104.054us | 1 | 1 | 100.00 | |
| sec_cm_ctr_local_esc | 1 | 1 | 100.00 | |||
| entropy_src_functional_errors | 3.000s | 30.604us | 1 | 1 | 100.00 | |
| sec_cm_esfinal_rdata_bus_consistency | 1 | 1 | 100.00 | |||
| entropy_src_functional_alerts | 9.000s | 679.873us | 1 | 1 | 100.00 | |
| sec_cm_tile_link_bus_integrity | 1 | 1 | 100.00 | |||
| entropy_src_tl_intg_err | 5.000s | 284.652us | 1 | 1 | 100.00 | |
| Testpoint | Test | Max Runtime | Sim Time | Pass | Total | % |
|---|---|---|---|---|---|---|
| external_health_tests | 1 | 1 | 100.00 | |||
| entropy_src_rng_with_xht_rsps | 251.000s | 14027.068us | 1 | 1 | 100.00 | |
| stress_all_with_rand_reset | 0 | 1 | 0.00 | |||
| entropy_src_stress_all_with_rand_reset | 25.000s | 2057.528us | 0 | 1 | 0.00 | |
| Test | seed | line | log context | |
|---|---|---|---|---|
| UVM_WARNING (uvm_reg_field.svh:1186) [RegModel] Trying to predict value of field 'observe_fifo_depth' while register 'entropy_src_reg_block.observe_fifo_depth' is being accessed | 1 test run | |||
| entropy_src_stress_all_with_rand_reset | 94480880424000291242529745090363891017616220765926750770862848816035155580406 | 125 |
UVM_FATAL @ 2057528092 ps: (entropy_src_scoreboard.sv:1599) [uvm_test_top.env.scoreboard] Check failed (ral.observe_fifo_depth.observe_fifo_depth.predict( ral.observe_fifo_depth.observe_fifo_depth.get_mirrored_value()-1, .kind(UVM_PREDICT_DIRECT)))
UVM_INFO @ 2057528092 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| Job timed out after * minutes | 1 test run | |||
| entropy_src_fw_ov | 25957827847139602187445306786247768905539719050075299631197329364394651212130 | None | ||