Simulation Results: hmac

 
01/09/2026 21:34:42 DVSim: v1.52.0 sha: 4e5c99d json Branch: master Tool: xcelium [24.03-s007]
Coverage statistics
  • Total
  • 69.37 %
  • code
  • 83.19 %
  • assert
  • 95.87 %
  • func
  • 29.06 %
  • block
  • 97.46 %
  • line
  • 98.39 %
  • branch
  • 93.64 %
  • toggle
  • 45.89 %
  • FSM
  • 94.83 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
V3
100.00%
unmapped
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
hmac_smoke 14.000s 1120.577us 1 1 100.00
csr_hw_reset 1 1 100.00
hmac_csr_hw_reset 2.000s 38.212us 1 1 100.00
csr_rw 1 1 100.00
hmac_csr_rw 2.000s 70.347us 1 1 100.00
csr_bit_bash 1 1 100.00
hmac_csr_bit_bash 8.000s 1136.148us 1 1 100.00
csr_aliasing 1 1 100.00
hmac_csr_aliasing 1.000s 117.665us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
hmac_csr_mem_rw_with_rand_reset 193.000s 19217.926us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
hmac_csr_rw 2.000s 70.347us 1 1 100.00
hmac_csr_aliasing 1.000s 117.665us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
long_msg 1 1 100.00
hmac_long_msg 98.000s 28204.254us 1 1 100.00
back_pressure 1 1 100.00
hmac_back_pressure 54.000s 7507.513us 1 1 100.00
test_vectors 6 6 100.00
hmac_test_sha256_vectors 13.000s 889.524us 1 1 100.00
hmac_test_sha384_vectors 23.000s 1086.433us 1 1 100.00
hmac_test_sha512_vectors 393.000s 12737.507us 1 1 100.00
hmac_test_hmac256_vectors 15.000s 843.465us 1 1 100.00
hmac_test_hmac384_vectors 14.000s 1888.050us 1 1 100.00
hmac_test_hmac512_vectors 13.000s 342.419us 1 1 100.00
burst_wr 1 1 100.00
hmac_burst_wr 7.000s 424.110us 1 1 100.00
datapath_stress 1 1 100.00
hmac_datapath_stress 156.000s 14707.248us 1 1 100.00
error 1 1 100.00
hmac_error 83.000s 73173.528us 1 1 100.00
wipe_secret 1 1 100.00
hmac_wipe_secret 174.000s 47755.040us 1 1 100.00
save_and_restore 6 6 100.00
hmac_smoke 14.000s 1120.577us 1 1 100.00
hmac_long_msg 98.000s 28204.254us 1 1 100.00
hmac_back_pressure 54.000s 7507.513us 1 1 100.00
hmac_datapath_stress 156.000s 14707.248us 1 1 100.00
hmac_burst_wr 7.000s 424.110us 1 1 100.00
hmac_stress_all 109.000s 39002.587us 1 1 100.00
fifo_empty_status_interrupt 11 11 100.00
hmac_smoke 14.000s 1120.577us 1 1 100.00
hmac_long_msg 98.000s 28204.254us 1 1 100.00
hmac_back_pressure 54.000s 7507.513us 1 1 100.00
hmac_datapath_stress 156.000s 14707.248us 1 1 100.00
hmac_wipe_secret 174.000s 47755.040us 1 1 100.00
hmac_test_sha256_vectors 13.000s 889.524us 1 1 100.00
hmac_test_sha384_vectors 23.000s 1086.433us 1 1 100.00
hmac_test_sha512_vectors 393.000s 12737.507us 1 1 100.00
hmac_test_hmac256_vectors 15.000s 843.465us 1 1 100.00
hmac_test_hmac384_vectors 14.000s 1888.050us 1 1 100.00
hmac_test_hmac512_vectors 13.000s 342.419us 1 1 100.00
wide_digest_configurable_key_length 14 14 100.00
hmac_smoke 14.000s 1120.577us 1 1 100.00
hmac_long_msg 98.000s 28204.254us 1 1 100.00
hmac_back_pressure 54.000s 7507.513us 1 1 100.00
hmac_datapath_stress 156.000s 14707.248us 1 1 100.00
hmac_burst_wr 7.000s 424.110us 1 1 100.00
hmac_error 83.000s 73173.528us 1 1 100.00
hmac_wipe_secret 174.000s 47755.040us 1 1 100.00
hmac_test_sha256_vectors 13.000s 889.524us 1 1 100.00
hmac_test_sha384_vectors 23.000s 1086.433us 1 1 100.00
hmac_test_sha512_vectors 393.000s 12737.507us 1 1 100.00
hmac_test_hmac256_vectors 15.000s 843.465us 1 1 100.00
hmac_test_hmac384_vectors 14.000s 1888.050us 1 1 100.00
hmac_test_hmac512_vectors 13.000s 342.419us 1 1 100.00
hmac_stress_all 109.000s 39002.587us 1 1 100.00
stress_all 1 1 100.00
hmac_stress_all 109.000s 39002.587us 1 1 100.00
alert_test 1 1 100.00
hmac_alert_test 1.000s 52.066us 1 1 100.00
intr_test 1 1 100.00
hmac_intr_test 1.000s 172.315us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
hmac_tl_errors 5.000s 80.129us 1 1 100.00
tl_d_illegal_access 1 1 100.00
hmac_tl_errors 5.000s 80.129us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
hmac_csr_hw_reset 2.000s 38.212us 1 1 100.00
hmac_csr_rw 2.000s 70.347us 1 1 100.00
hmac_csr_aliasing 1.000s 117.665us 1 1 100.00
hmac_same_csr_outstanding 4.000s 146.650us 1 1 100.00
tl_d_partial_access 4 4 100.00
hmac_csr_hw_reset 2.000s 38.212us 1 1 100.00
hmac_csr_rw 2.000s 70.347us 1 1 100.00
hmac_csr_aliasing 1.000s 117.665us 1 1 100.00
hmac_same_csr_outstanding 4.000s 146.650us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
hmac_sec_cm 2.000s 323.143us 1 1 100.00
hmac_tl_intg_err 4.000s 1669.566us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
hmac_tl_intg_err 4.000s 1669.566us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
write_config_and_secret_key_during_msg_wr 1 1 100.00
hmac_smoke 14.000s 1120.577us 1 1 100.00
stress_reset 1 1 100.00
hmac_stress_reset 4.000s 3172.685us 1 1 100.00
stress_all_with_rand_reset 1 1 100.00
hmac_stress_all_with_rand_reset 81.000s 41323.069us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
Unmapped 1 1 100.00
hmac_directed 3.000s 128.633us 1 1 100.00