Simulation Results

Simulation Results: i2c

01/09/2026 21:34:42 DVSim: v1.52.0 sha: 4e5c99d json Branch: master Tool: xcelium [24.03-s007]

Coverage statistics

Total
88.42 %

code
86.41 %

assert
97.46 %

func
81.38 %

block
96.19 %

line
95.59 %

branch
93.19 %

toggle
72.68 %

FSM
84.17 %

Validation stages

V1		100.00%
V2		85.37%
V2S		100.00%
V3		0.00%

7/7 passed

100.00 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
host_smoke				1	1	100.00
	i2c_host_smoke	125.000s	19752.022us	1	1	100.00
target_smoke				1	1	100.00
	i2c_target_smoke	9.000s	1260.675us	1	1	100.00
csr_hw_reset				1	1	100.00
	i2c_csr_hw_reset	1.000s	19.159us	1	1	100.00
csr_rw				1	1	100.00
	i2c_csr_rw	1.000s	161.505us	1	1	100.00
csr_bit_bash				1	1	100.00
	i2c_csr_bit_bash	4.000s	174.626us	1	1	100.00
csr_aliasing				1	1	100.00
	i2c_csr_aliasing	2.000s	26.721us	1	1	100.00
csr_mem_rw_with_rand_reset				1	1	100.00
	i2c_csr_mem_rw_with_rand_reset	1.000s	33.764us	1	1	100.00
regwen_csr_and_corresponding_lockable_csr				2	2	100.00
	i2c_csr_rw	1.000s	161.505us	1	1	100.00
	i2c_csr_aliasing	2.000s	26.721us	1	1	100.00

35/41 passed

85.37 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
host_error_intr				0	1	0.00
	i2c_host_error_intr	2.000s	121.398us	0	1	0.00
host_stress_all				0	1	0.00
	i2c_host_stress_all	35.000s	9732.674us	0	1	0.00
host_maxperf				1	1	100.00
	i2c_host_perf	179.000s	27804.882us	1	1	100.00
host_override				1	1	100.00
	i2c_host_override	2.000s	107.510us	1	1	100.00
host_fifo_watermark				1	1	100.00
	i2c_host_fifo_watermark	2474.000s	3820.273us	1	1	100.00
host_fifo_overflow				1	1	100.00
	i2c_host_fifo_overflow	701.000s	1491.046us	1	1	100.00
host_fifo_reset				3	3	100.00
	i2c_host_fifo_reset_fmt	2.000s	105.555us	1	1	100.00
	i2c_host_fifo_fmt_empty	36.000s	1945.594us	1	1	100.00
	i2c_host_fifo_reset_rx	6.000s	186.696us	1	1	100.00
host_fifo_full				1	1	100.00
	i2c_host_fifo_full	52.000s	4744.025us	1	1	100.00
host_timeout				1	1	100.00
	i2c_host_stretch_timeout	33.000s	5868.480us	1	1	100.00
i2c_host_mode_toggle				1	1	100.00
	i2c_host_mode_toggle	4.000s	283.530us	1	1	100.00
target_glitch				0	1	0.00
	i2c_target_glitch	4.000s	2160.920us	0	1	0.00
target_stress_all				0	1	0.00
	i2c_target_stress_all	3601.000s	0.000us	0	1	0.00
target_maxperf				1	1	100.00
	i2c_target_perf	5.000s	541.295us	1	1	100.00
target_fifo_empty				2	2	100.00
	i2c_target_stress_rd	17.000s	4297.400us	1	1	100.00
	i2c_target_intr_smoke	8.000s	3732.132us	1	1	100.00
target_fifo_reset				2	2	100.00
	i2c_target_fifo_reset_acq	2.000s	146.786us	1	1	100.00
	i2c_target_fifo_reset_tx	3.000s	329.882us	1	1	100.00
target_fifo_full				2	3	66.67
	i2c_target_stress_wr	891.000s	40899.331us	1	1	100.00
	i2c_target_stress_rd	17.000s	4297.400us	1	1	100.00
	i2c_target_intr_stress_wr	3602.301s	0.000us	0	1	0.00
target_timeout				1	1	100.00
	i2c_target_timeout	10.000s	4089.038us	1	1	100.00
target_clock_stretch				1	1	100.00
	i2c_target_stretch	466.000s	7339.724us	1	1	100.00
bad_address				1	1	100.00
	i2c_target_bad_addr	5.000s	682.360us	1	1	100.00
target_mode_glitch				0	1	0.00
	i2c_target_hrst	25.000s	10413.706us	0	1	0.00
target_fifo_watermark				2	2	100.00
	i2c_target_fifo_watermarks_acq	4.000s	1870.923us	1	1	100.00
	i2c_target_fifo_watermarks_tx	3.000s	277.316us	1	1	100.00
host_mode_config_perf				2	2	100.00
	i2c_host_perf	179.000s	27804.882us	1	1	100.00
	i2c_host_perf_precise	6.000s	227.131us	1	1	100.00
host_mode_clock_stretching				1	1	100.00
	i2c_host_stretch_timeout	33.000s	5868.480us	1	1	100.00
target_mode_tx_stretch_ctrl				1	1	100.00
	i2c_target_tx_stretch_ctrl	4.000s	130.351us	1	1	100.00
target_mode_nack_generation				3	3	100.00
	i2c_target_nack_acqfull	5.000s	943.372us	1	1	100.00
	i2c_target_nack_acqfull_addr	5.000s	446.478us	1	1	100.00
	i2c_target_nack_txstretch	3.000s	899.955us	1	1	100.00
host_mode_halt_on_nak				1	1	100.00
	i2c_host_may_nack	3.000s	438.590us	1	1	100.00
target_mode_smbus_maxlen				1	1	100.00
	i2c_target_smbus_maxlen	4.000s	370.259us	1	1	100.00
alert_test				1	1	100.00
	i2c_alert_test	1.000s	49.356us	1	1	100.00
intr_test				1	1	100.00
	i2c_intr_test	1.000s	17.267us	1	1	100.00
tl_d_oob_addr_access				1	1	100.00
	i2c_tl_errors	2.000s	47.680us	1	1	100.00
tl_d_illegal_access				1	1	100.00
	i2c_tl_errors	2.000s	47.680us	1	1	100.00
tl_d_outstanding_access				4	4	100.00
	i2c_csr_hw_reset	1.000s	19.159us	1	1	100.00
	i2c_csr_rw	1.000s	161.505us	1	1	100.00
	i2c_csr_aliasing	2.000s	26.721us	1	1	100.00
	i2c_same_csr_outstanding	2.000s	30.216us	1	1	100.00
tl_d_partial_access				4	4	100.00
	i2c_csr_hw_reset	1.000s	19.159us	1	1	100.00
	i2c_csr_rw	1.000s	161.505us	1	1	100.00
	i2c_csr_aliasing	2.000s	26.721us	1	1	100.00
	i2c_same_csr_outstanding	2.000s	30.216us	1	1	100.00

V2S

2/2 passed

100.00 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
tl_intg_err				2	2	100.00
	i2c_tl_intg_err	2.000s	177.791us	1	1	100.00
	i2c_sec_cm	1.000s	504.625us	1	1	100.00
sec_cm_bus_integrity				1	1	100.00
	i2c_tl_intg_err	2.000s	177.791us	1	1	100.00

0/3 passed

0.00 %

Testpoint	Test	Max Runtime	Sim Time	Total
host_stress_all_with_rand_reset				1
	i2c_host_stress_all_with_rand_reset	20.000s	8379.242us	1
target_error_intr				1
	i2c_target_unexp_stop	2.000s	98.154us	1
target_stress_all_with_rand_reset				1
	i2c_target_stress_all_with_rand_reset	26.000s	781.182us	1

Error Messages

	Test	seed	line	log context
UVM_ERROR sequencer [sequencer] Get_next_item called twice without item_done or get in between				2 test runs
	i2c_host_error_intr	65649448147121545587449551136870755443304887290588936874577457021128504033831	113	UVM_INFO @ 121397813 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	i2c_host_stress_all	78135265440973906103327577748976753003742682108152726864901629421149353189272	119	UVM_INFO @ 9732674298 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
Job timed out after * minutes				2 test runs
	i2c_target_intr_stress_wr	55148604021642052202440010128408889836674159929371427653718073412477774880540	None
	i2c_target_stress_all	36801856334766372405322624211351258566286730378047942478683928774570093767629	None
UVM_ERROR (cip_base_vseq.sv:1297) [i2c_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses.				2 test runs
	i2c_host_stress_all_with_rand_reset	81681466279980443620242393855303104847708470029911843749514925446818014875500	101	UVM_INFO @ 8379242320 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	i2c_target_stress_all_with_rand_reset	82350090239328044099533020604435429263529735184307621585579766041086943900018	102	UVM_INFO @ 781182237 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_ERROR sequencer [sequencer] get_next_item/try_next_item called twice without item_done or get in between				1 test run
	i2c_target_glitch	53787853149584123905577941965927492860410178852893945070111417410357001291317	93	UVM_INFO @ 2160919597 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_ERROR (i2c_scoreboard.sv:680) [scoreboard] Check failed obs.data_q[i] == exp.data_q[i] (* [] vs [*])				1 test run
	i2c_target_unexp_stop	27293603545966835021440855563882134638099769919255601966850976854078106727692	87	UVM_INFO @ 98153999 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_FATAL (i2c_target_hrst_vseq.sv:107) [target_hrst_vseq] wait timeout occurred!				1 test run
	i2c_target_hrst	73524404559051314521816400725959012950723091234593958854144455757533478232142	88	UVM_INFO @ 10413705782 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---