Simulation Results: lc_ctrl/volatile_unlock_disabled

 
01/09/2026 21:34:42 DVSim: v1.52.0 sha: 4e5c99d json Branch: master Tool: xcelium [24.03-s007]
Coverage statistics
  • Total
  • 87.95 %
  • code
  • 89.82 %
  • assert
  • 95.97 %
  • func
  • 78.06 %
  • block
  • 95.76 %
  • line
  • 96.39 %
  • branch
  • 89.20 %
  • toggle
  • 83.22 %
  • FSM
  • 90.48 %
Validation stages
V1
100.00%
V2
70.00%
V2S
60.00%
V3
0.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
lc_ctrl_smoke 2.000s 66.021us 1 1 100.00
csr_hw_reset 1 1 100.00
lc_ctrl_csr_hw_reset 7.000s 29.141us 1 1 100.00
csr_rw 1 1 100.00
lc_ctrl_csr_rw 2.000s 53.827us 1 1 100.00
csr_bit_bash 1 1 100.00
lc_ctrl_csr_bit_bash 2.000s 86.459us 1 1 100.00
csr_aliasing 1 1 100.00
lc_ctrl_csr_aliasing 2.000s 15.511us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
lc_ctrl_csr_mem_rw_with_rand_reset 2.000s 56.335us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
lc_ctrl_csr_rw 2.000s 53.827us 1 1 100.00
lc_ctrl_csr_aliasing 2.000s 15.511us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
state_post_trans 0 1 0.00
lc_ctrl_state_post_trans 3600.000s 0.000us 0 1 0.00
regwen_during_op 1 1 100.00
lc_ctrl_regwen_during_op 5.000s 241.325us 1 1 100.00
rand_wr_claim_transition_if 1 1 100.00
lc_ctrl_claim_transition_if 2.000s 37.423us 1 1 100.00
lc_prog_failure 0 1 0.00
lc_ctrl_prog_failure 3601.000s 0.000us 0 1 0.00
lc_state_failure 0 1 0.00
lc_ctrl_state_failure 3600.000s 0.000us 0 1 0.00
lc_errors 0 1 0.00
lc_ctrl_errors 3600.000s 0.000us 0 1 0.00
security_escalation 1 7 14.29
lc_ctrl_state_failure 3600.000s 0.000us 0 1 0.00
lc_ctrl_prog_failure 3601.000s 0.000us 0 1 0.00
lc_ctrl_errors 3600.000s 0.000us 0 1 0.00
lc_ctrl_security_escalation 5.000s 1180.461us 1 1 100.00
lc_ctrl_jtag_state_failure 3.000s 201.721us 0 1 0.00
lc_ctrl_jtag_prog_failure 3600.000s 0.000us 0 1 0.00
lc_ctrl_jtag_errors 3600.000s 0.000us 0 1 0.00
jtag_access 10 13 76.92
lc_ctrl_jtag_smoke 6.000s 364.031us 1 1 100.00
lc_ctrl_jtag_state_post_trans 3600.000s 0.000us 0 1 0.00
lc_ctrl_jtag_prog_failure 3600.000s 0.000us 0 1 0.00
lc_ctrl_jtag_errors 3600.000s 0.000us 0 1 0.00
lc_ctrl_jtag_access 7.000s 880.411us 1 1 100.00
lc_ctrl_jtag_regwen_during_op 10.000s 2871.070us 1 1 100.00
lc_ctrl_jtag_csr_hw_reset 3.000s 118.160us 1 1 100.00
lc_ctrl_jtag_csr_rw 2.000s 53.595us 1 1 100.00
lc_ctrl_jtag_csr_bit_bash 10.000s 15134.271us 1 1 100.00
lc_ctrl_jtag_csr_aliasing 3.000s 200.437us 1 1 100.00
lc_ctrl_jtag_same_csr_outstanding 2.000s 710.658us 1 1 100.00
lc_ctrl_jtag_csr_mem_rw_with_rand_reset 2.000s 104.869us 1 1 100.00
lc_ctrl_jtag_alert_test 3.000s 444.374us 1 1 100.00
jtag_priority 1 1 100.00
lc_ctrl_jtag_priority 4.000s 175.568us 1 1 100.00
lc_ctrl_volatile_unlock 1 1 100.00
lc_ctrl_volatile_unlock_smoke 2.000s 14.407us 1 1 100.00
stress_all 0 1 0.00
lc_ctrl_stress_all 10802.213s 0.000us 0 1 0.00
alert_test 1 1 100.00
lc_ctrl_alert_test 2.000s 38.898us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
lc_ctrl_tl_errors 4.000s 137.135us 1 1 100.00
tl_d_illegal_access 1 1 100.00
lc_ctrl_tl_errors 4.000s 137.135us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
lc_ctrl_csr_hw_reset 7.000s 29.141us 1 1 100.00
lc_ctrl_csr_rw 2.000s 53.827us 1 1 100.00
lc_ctrl_csr_aliasing 2.000s 15.511us 1 1 100.00
lc_ctrl_same_csr_outstanding 2.000s 131.217us 1 1 100.00
tl_d_partial_access 4 4 100.00
lc_ctrl_csr_hw_reset 7.000s 29.141us 1 1 100.00
lc_ctrl_csr_rw 2.000s 53.827us 1 1 100.00
lc_ctrl_csr_aliasing 2.000s 15.511us 1 1 100.00
lc_ctrl_same_csr_outstanding 2.000s 131.217us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
lc_ctrl_sec_cm 4.000s 295.977us 1 1 100.00
lc_ctrl_tl_intg_err 4.000s 225.190us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
lc_ctrl_tl_intg_err 4.000s 225.190us 1 1 100.00
sec_cm_transition_config_regwen 1 1 100.00
lc_ctrl_regwen_during_op 5.000s 241.325us 1 1 100.00
sec_cm_manuf_state_sparse 1 2 50.00
lc_ctrl_state_failure 3600.000s 0.000us 0 1 0.00
lc_ctrl_sec_cm 4.000s 295.977us 1 1 100.00
sec_cm_transition_ctr_sparse 1 2 50.00
lc_ctrl_state_failure 3600.000s 0.000us 0 1 0.00
lc_ctrl_sec_cm 4.000s 295.977us 1 1 100.00
sec_cm_manuf_state_bkgn_chk 1 2 50.00
lc_ctrl_state_failure 3600.000s 0.000us 0 1 0.00
lc_ctrl_sec_cm 4.000s 295.977us 1 1 100.00
sec_cm_transition_ctr_bkgn_chk 1 2 50.00
lc_ctrl_state_failure 3600.000s 0.000us 0 1 0.00
lc_ctrl_sec_cm 4.000s 295.977us 1 1 100.00
sec_cm_state_config_sparse 1 2 50.00
lc_ctrl_state_failure 3600.000s 0.000us 0 1 0.00
lc_ctrl_sec_cm 4.000s 295.977us 1 1 100.00
sec_cm_main_fsm_sparse 1 2 50.00
lc_ctrl_state_failure 3600.000s 0.000us 0 1 0.00
lc_ctrl_sec_cm 4.000s 295.977us 1 1 100.00
sec_cm_kmac_fsm_sparse 1 2 50.00
lc_ctrl_state_failure 3600.000s 0.000us 0 1 0.00
lc_ctrl_sec_cm 4.000s 295.977us 1 1 100.00
sec_cm_main_fsm_local_esc 1 2 50.00
lc_ctrl_state_failure 3600.000s 0.000us 0 1 0.00
lc_ctrl_sec_cm 4.000s 295.977us 1 1 100.00
sec_cm_main_fsm_global_esc 1 1 100.00
lc_ctrl_security_escalation 5.000s 1180.461us 1 1 100.00
sec_cm_main_ctrl_flow_consistency 0 2 0.00
lc_ctrl_state_post_trans 3600.000s 0.000us 0 1 0.00
lc_ctrl_jtag_state_post_trans 3600.000s 0.000us 0 1 0.00
sec_cm_intersig_mubi 0 1 0.00
lc_ctrl_sec_mubi 3600.000s 0.000us 0 1 0.00
sec_cm_token_valid_ctrl_mubi 0 1 0.00
lc_ctrl_sec_mubi 3600.000s 0.000us 0 1 0.00
sec_cm_token_digest 1 1 100.00
lc_ctrl_sec_token_digest 6.000s 1379.740us 1 1 100.00
sec_cm_token_mux_ctrl_redun 1 1 100.00
lc_ctrl_sec_token_mux 6.000s 363.310us 1 1 100.00
sec_cm_token_valid_mux_redun 1 1 100.00
lc_ctrl_sec_token_mux 6.000s 363.310us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 0 1 0.00
lc_ctrl_stress_all_with_rand_reset 3600.000s 0.000us 0 1 0.00

Error Messages

   Test seed line log context
Job timed out after * minutes 10 test runs
lc_ctrl_state_failure 26695303434849573816025205586607805835111843909861138922275999538603380772058 None
lc_ctrl_state_post_trans 2639318690303401321658722453836527791720303572062393423236994482666589495623 None
lc_ctrl_prog_failure 13941263467947771599502094904799847498374183443523841402131964821436747583759 None
lc_ctrl_errors 81984917710106592699675828751719430125161341311718692855125193131195497631207 None
lc_ctrl_jtag_state_post_trans 59171048460066816912310656396307224010485589324213674073043530662191802191122 None
lc_ctrl_jtag_prog_failure 46721012352533578398185332527801295554589378759675896463981353121821556957568 None
lc_ctrl_jtag_errors 55586368132335816071011016283324684732992123448635831572034609662645800166062 None
lc_ctrl_sec_mubi 43366315290949215571786412062107235159760443720576236573847198375041749716441 None
lc_ctrl_stress_all 60330000216024515558547651976886838567648699905916065826233020648784778957036 None
lc_ctrl_stress_all_with_rand_reset 28632908819903458751152801505886060539704144734223691858188742332584675843809 None
UVM_ERROR (cip_base_scoreboard.sv:256) scoreboard [scoreboard] alert fatal_state_error has unexpected timeout error 1 test run
lc_ctrl_jtag_state_failure 2774016140845043446704558545255693981914514584551341651299142841164348655734 175
UVM_INFO @ 201721475 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---