Simulation Results: lc_ctrl/volatile_unlock_enabled

 
01/09/2026 21:34:42 DVSim: v1.52.0 sha: 4e5c99d json Branch: master Tool: xcelium [24.03-s007]
Coverage statistics
  • Total
  • 88.83 %
  • code
  • 90.62 %
  • assert
  • 96.83 %
  • func
  • 79.03 %
  • block
  • 96.34 %
  • line
  • 97.21 %
  • branch
  • 90.73 %
  • toggle
  • 79.31 %
  • FSM
  • 95.24 %
Validation stages
V1
100.00%
V2
73.33%
V2S
60.00%
V3
0.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
lc_ctrl_smoke 2.000s 468.811us 1 1 100.00
csr_hw_reset 1 1 100.00
lc_ctrl_csr_hw_reset 1.000s 81.723us 1 1 100.00
csr_rw 1 1 100.00
lc_ctrl_csr_rw 2.000s 38.504us 1 1 100.00
csr_bit_bash 1 1 100.00
lc_ctrl_csr_bit_bash 3.000s 125.769us 1 1 100.00
csr_aliasing 1 1 100.00
lc_ctrl_csr_aliasing 1.000s 33.549us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
lc_ctrl_csr_mem_rw_with_rand_reset 2.000s 124.261us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
lc_ctrl_csr_rw 2.000s 38.504us 1 1 100.00
lc_ctrl_csr_aliasing 1.000s 33.549us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
state_post_trans 0 1 0.00
lc_ctrl_state_post_trans 3600.000s 0.000us 0 1 0.00
regwen_during_op 1 1 100.00
lc_ctrl_regwen_during_op 9.000s 966.301us 1 1 100.00
rand_wr_claim_transition_if 1 1 100.00
lc_ctrl_claim_transition_if 1.000s 45.931us 1 1 100.00
lc_prog_failure 1 1 100.00
lc_ctrl_prog_failure 2.000s 30.970us 1 1 100.00
lc_state_failure 0 1 0.00
lc_ctrl_state_failure 3600.000s 0.000us 0 1 0.00
lc_errors 0 1 0.00
lc_ctrl_errors 3600.000s 0.000us 0 1 0.00
security_escalation 2 7 28.57
lc_ctrl_state_failure 3600.000s 0.000us 0 1 0.00
lc_ctrl_prog_failure 2.000s 30.970us 1 1 100.00
lc_ctrl_errors 3600.000s 0.000us 0 1 0.00
lc_ctrl_security_escalation 5.000s 693.626us 1 1 100.00
lc_ctrl_jtag_state_failure 3600.000s 0.000us 0 1 0.00
lc_ctrl_jtag_prog_failure 3600.000s 0.000us 0 1 0.00
lc_ctrl_jtag_errors 3601.000s 0.000us 0 1 0.00
jtag_access 10 13 76.92
lc_ctrl_jtag_smoke 5.000s 533.119us 1 1 100.00
lc_ctrl_jtag_state_post_trans 2.000s 98.896us 0 1 0.00
lc_ctrl_jtag_prog_failure 3600.000s 0.000us 0 1 0.00
lc_ctrl_jtag_errors 3601.000s 0.000us 0 1 0.00
lc_ctrl_jtag_access 6.000s 441.925us 1 1 100.00
lc_ctrl_jtag_regwen_during_op 10.000s 1356.624us 1 1 100.00
lc_ctrl_jtag_csr_hw_reset 2.000s 202.038us 1 1 100.00
lc_ctrl_jtag_csr_rw 2.000s 72.326us 1 1 100.00
lc_ctrl_jtag_csr_bit_bash 8.000s 1582.659us 1 1 100.00
lc_ctrl_jtag_csr_aliasing 3.000s 328.366us 1 1 100.00
lc_ctrl_jtag_same_csr_outstanding 2.000s 156.831us 1 1 100.00
lc_ctrl_jtag_csr_mem_rw_with_rand_reset 2.000s 130.156us 1 1 100.00
lc_ctrl_jtag_alert_test 3.000s 240.365us 1 1 100.00
jtag_priority 1 1 100.00
lc_ctrl_jtag_priority 4.000s 1163.871us 1 1 100.00
lc_ctrl_volatile_unlock 1 1 100.00
lc_ctrl_volatile_unlock_smoke 2.000s 50.404us 1 1 100.00
stress_all 0 1 0.00
lc_ctrl_stress_all 10802.213s 0.000us 0 1 0.00
alert_test 1 1 100.00
lc_ctrl_alert_test 2.000s 62.028us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
lc_ctrl_tl_errors 2.000s 23.631us 1 1 100.00
tl_d_illegal_access 1 1 100.00
lc_ctrl_tl_errors 2.000s 23.631us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
lc_ctrl_csr_hw_reset 1.000s 81.723us 1 1 100.00
lc_ctrl_csr_rw 2.000s 38.504us 1 1 100.00
lc_ctrl_csr_aliasing 1.000s 33.549us 1 1 100.00
lc_ctrl_same_csr_outstanding 1.000s 52.014us 1 1 100.00
tl_d_partial_access 4 4 100.00
lc_ctrl_csr_hw_reset 1.000s 81.723us 1 1 100.00
lc_ctrl_csr_rw 2.000s 38.504us 1 1 100.00
lc_ctrl_csr_aliasing 1.000s 33.549us 1 1 100.00
lc_ctrl_same_csr_outstanding 1.000s 52.014us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
lc_ctrl_sec_cm 3.000s 264.165us 1 1 100.00
lc_ctrl_tl_intg_err 2.000s 159.668us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
lc_ctrl_tl_intg_err 2.000s 159.668us 1 1 100.00
sec_cm_transition_config_regwen 1 1 100.00
lc_ctrl_regwen_during_op 9.000s 966.301us 1 1 100.00
sec_cm_manuf_state_sparse 1 2 50.00
lc_ctrl_state_failure 3600.000s 0.000us 0 1 0.00
lc_ctrl_sec_cm 3.000s 264.165us 1 1 100.00
sec_cm_transition_ctr_sparse 1 2 50.00
lc_ctrl_state_failure 3600.000s 0.000us 0 1 0.00
lc_ctrl_sec_cm 3.000s 264.165us 1 1 100.00
sec_cm_manuf_state_bkgn_chk 1 2 50.00
lc_ctrl_state_failure 3600.000s 0.000us 0 1 0.00
lc_ctrl_sec_cm 3.000s 264.165us 1 1 100.00
sec_cm_transition_ctr_bkgn_chk 1 2 50.00
lc_ctrl_state_failure 3600.000s 0.000us 0 1 0.00
lc_ctrl_sec_cm 3.000s 264.165us 1 1 100.00
sec_cm_state_config_sparse 1 2 50.00
lc_ctrl_state_failure 3600.000s 0.000us 0 1 0.00
lc_ctrl_sec_cm 3.000s 264.165us 1 1 100.00
sec_cm_main_fsm_sparse 1 2 50.00
lc_ctrl_state_failure 3600.000s 0.000us 0 1 0.00
lc_ctrl_sec_cm 3.000s 264.165us 1 1 100.00
sec_cm_kmac_fsm_sparse 1 2 50.00
lc_ctrl_state_failure 3600.000s 0.000us 0 1 0.00
lc_ctrl_sec_cm 3.000s 264.165us 1 1 100.00
sec_cm_main_fsm_local_esc 1 2 50.00
lc_ctrl_state_failure 3600.000s 0.000us 0 1 0.00
lc_ctrl_sec_cm 3.000s 264.165us 1 1 100.00
sec_cm_main_fsm_global_esc 1 1 100.00
lc_ctrl_security_escalation 5.000s 693.626us 1 1 100.00
sec_cm_main_ctrl_flow_consistency 0 2 0.00
lc_ctrl_state_post_trans 3600.000s 0.000us 0 1 0.00
lc_ctrl_jtag_state_post_trans 2.000s 98.896us 0 1 0.00
sec_cm_intersig_mubi 0 1 0.00
lc_ctrl_sec_mubi 3600.000s 0.000us 0 1 0.00
sec_cm_token_valid_ctrl_mubi 0 1 0.00
lc_ctrl_sec_mubi 3600.000s 0.000us 0 1 0.00
sec_cm_token_digest 1 1 100.00
lc_ctrl_sec_token_digest 7.000s 315.429us 1 1 100.00
sec_cm_token_mux_ctrl_redun 1 1 100.00
lc_ctrl_sec_token_mux 6.000s 367.099us 1 1 100.00
sec_cm_token_valid_mux_redun 1 1 100.00
lc_ctrl_sec_token_mux 6.000s 367.099us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 0 1 0.00
lc_ctrl_stress_all_with_rand_reset 3601.000s 0.000us 0 1 0.00

Error Messages

   Test seed line log context
Job timed out after * minutes 9 test runs
lc_ctrl_state_failure 27227096819315347251935023591664135824819423920652782535356865310814500733067 None
lc_ctrl_state_post_trans 48112991105369642970147612580917608732082861883759950494209502961961424207725 None
lc_ctrl_errors 14553572592792315075273970817675600693431937721343700213529720041538282845621 None
lc_ctrl_jtag_state_failure 68415098614749765728043289705852688184214753617803931153196920594634217091793 None
lc_ctrl_jtag_prog_failure 93528306662798799349490636768324653265921376000344464713452001361565224662657 None
lc_ctrl_jtag_errors 33287385838234769827852100676423615773952083501549052657211188251226939540882 None
lc_ctrl_sec_mubi 70789177787964717507362269849002130064307821450959387724049767999625129243931 None
lc_ctrl_stress_all 61580076684705606047690578177761190674684681419295384174508070701367249130054 None
lc_ctrl_stress_all_with_rand_reset 56874963640490551609442942552376513653181021795211002877269366297249196962009 None
UVM_ERROR (cip_base_scoreboard.sv:256) scoreboard [scoreboard] alert fatal_state_error has unexpected timeout error 1 test run
lc_ctrl_jtag_state_post_trans 108718411908815379888472602384205832735264340465197600675966043080651729205793 177
UVM_INFO @ 98895628 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---