Simulation Results: otp_ctrl

 
01/09/2026 21:34:42 DVSim: v1.52.0 sha: 4e5c99d json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 73.40 %
  • code
  • 72.99 %
  • assert
  • 93.76 %
  • func
  • 53.44 %
  • line
  • 87.44 %
  • branch
  • 84.35 %
  • cond
  • 86.17 %
  • toggle
  • 68.83 %
  • FSM
  • 38.14 %
Validation stages
V1
88.89%
V2
65.00%
V2S
66.67%
V3
0.00%
Testpoint Test Max Runtime Sim Time Pass Total %
wake_up 1 1 100.00
otp_ctrl_wake_up 2.390s 56.335us 1 1 100.00
smoke 1 1 100.00
otp_ctrl_smoke 7.070s 393.051us 1 1 100.00
csr_hw_reset 1 1 100.00
otp_ctrl_csr_hw_reset 3.240s 249.064us 1 1 100.00
csr_rw 1 1 100.00
otp_ctrl_csr_rw 2.450s 80.448us 1 1 100.00
csr_bit_bash 1 1 100.00
otp_ctrl_csr_bit_bash 9.180s 1214.657us 1 1 100.00
csr_aliasing 1 1 100.00
otp_ctrl_csr_aliasing 2.570s 746.848us 1 1 100.00
csr_mem_rw_with_rand_reset 0 1 0.00
otp_ctrl_csr_mem_rw_with_rand_reset 2.600s 65.960us 0 1 0.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
otp_ctrl_csr_rw 2.450s 80.448us 1 1 100.00
otp_ctrl_csr_aliasing 2.570s 746.848us 1 1 100.00
mem_walk 1 1 100.00
otp_ctrl_mem_walk 3.160s 634.791us 1 1 100.00
mem_partial_access 1 1 100.00
otp_ctrl_mem_partial_access 1.640s 94.694us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
dai_access_partition_walk 0 1 0.00
otp_ctrl_partition_walk 171.630s 13565.165us 0 1 0.00
init_fail 0 1 0.00
otp_ctrl_init_fail 4.110s 287.001us 0 1 0.00
partition_check 1 2 50.00
otp_ctrl_background_chks 45.880s 6574.170us 0 1 0.00
otp_ctrl_check_fail 16.770s 10760.994us 1 1 100.00
regwen_during_otp_init 1 1 100.00
otp_ctrl_regwen 9.560s 300.112us 1 1 100.00
partition_lock 0 1 0.00
otp_ctrl_dai_lock 2.990s 184.124us 0 1 0.00
interface_key_check 1 1 100.00
otp_ctrl_parallel_key_req 7.740s 370.220us 1 1 100.00
lc_interactions 2 2 100.00
otp_ctrl_parallel_lc_req 13.820s 1120.941us 1 1 100.00
otp_ctrl_parallel_lc_esc 35.320s 9729.424us 1 1 100.00
otp_dai_errors 1 1 100.00
otp_ctrl_dai_errs 51.640s 2849.678us 1 1 100.00
otp_macro_errors 0 1 0.00
otp_ctrl_macro_errs 8.390s 705.444us 0 1 0.00
test_access 0 1 0.00
otp_ctrl_test_access 16.220s 580.923us 0 1 0.00
stress_all 0 1 0.00
otp_ctrl_stress_all 3.960s 107.133us 0 1 0.00
intr_test 1 1 100.00
otp_ctrl_intr_test 2.600s 93.179us 1 1 100.00
alert_test 1 1 100.00
otp_ctrl_alert_test 3.920s 1036.451us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
otp_ctrl_tl_errors 5.170s 502.322us 1 1 100.00
tl_d_illegal_access 1 1 100.00
otp_ctrl_tl_errors 5.170s 502.322us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
otp_ctrl_csr_hw_reset 3.240s 249.064us 1 1 100.00
otp_ctrl_csr_rw 2.450s 80.448us 1 1 100.00
otp_ctrl_csr_aliasing 2.570s 746.848us 1 1 100.00
otp_ctrl_same_csr_outstanding 5.010s 560.147us 1 1 100.00
tl_d_partial_access 4 4 100.00
otp_ctrl_csr_hw_reset 3.240s 249.064us 1 1 100.00
otp_ctrl_csr_rw 2.450s 80.448us 1 1 100.00
otp_ctrl_csr_aliasing 2.570s 746.848us 1 1 100.00
otp_ctrl_same_csr_outstanding 5.010s 560.147us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
sec_cm_additional_check 1 1 100.00
otp_ctrl_sec_cm 488.010s 37188.481us 1 1 100.00
tl_intg_err 2 2 100.00
otp_ctrl_sec_cm 488.010s 37188.481us 1 1 100.00
otp_ctrl_tl_intg_err 20.770s 11471.497us 1 1 100.00
prim_count_check 1 1 100.00
otp_ctrl_sec_cm 488.010s 37188.481us 1 1 100.00
prim_fsm_check 1 1 100.00
otp_ctrl_sec_cm 488.010s 37188.481us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
otp_ctrl_tl_intg_err 20.770s 11471.497us 1 1 100.00
sec_cm_secret_mem_scramble 1 1 100.00
otp_ctrl_smoke 7.070s 393.051us 1 1 100.00
sec_cm_part_mem_digest 1 1 100.00
otp_ctrl_smoke 7.070s 393.051us 1 1 100.00
sec_cm_dai_fsm_sparse 1 1 100.00
otp_ctrl_sec_cm 488.010s 37188.481us 1 1 100.00
sec_cm_kdi_fsm_sparse 1 1 100.00
otp_ctrl_sec_cm 488.010s 37188.481us 1 1 100.00
sec_cm_lci_fsm_sparse 1 1 100.00
otp_ctrl_sec_cm 488.010s 37188.481us 1 1 100.00
sec_cm_part_fsm_sparse 1 1 100.00
otp_ctrl_sec_cm 488.010s 37188.481us 1 1 100.00
sec_cm_scrmbl_fsm_sparse 1 1 100.00
otp_ctrl_sec_cm 488.010s 37188.481us 1 1 100.00
sec_cm_timer_fsm_sparse 1 1 100.00
otp_ctrl_sec_cm 488.010s 37188.481us 1 1 100.00
sec_cm_dai_ctr_redun 1 1 100.00
otp_ctrl_sec_cm 488.010s 37188.481us 1 1 100.00
sec_cm_kdi_seed_ctr_redun 1 1 100.00
otp_ctrl_sec_cm 488.010s 37188.481us 1 1 100.00
sec_cm_kdi_entropy_ctr_redun 1 1 100.00
otp_ctrl_sec_cm 488.010s 37188.481us 1 1 100.00
sec_cm_lci_ctr_redun 1 1 100.00
otp_ctrl_sec_cm 488.010s 37188.481us 1 1 100.00
sec_cm_part_ctr_redun 1 1 100.00
otp_ctrl_sec_cm 488.010s 37188.481us 1 1 100.00
sec_cm_scrmbl_ctr_redun 1 1 100.00
otp_ctrl_sec_cm 488.010s 37188.481us 1 1 100.00
sec_cm_timer_integ_ctr_redun 1 1 100.00
otp_ctrl_sec_cm 488.010s 37188.481us 1 1 100.00
sec_cm_timer_cnsty_ctr_redun 1 1 100.00
otp_ctrl_sec_cm 488.010s 37188.481us 1 1 100.00
sec_cm_timer_lfsr_redun 1 1 100.00
otp_ctrl_sec_cm 488.010s 37188.481us 1 1 100.00
sec_cm_dai_fsm_local_esc 2 2 100.00
otp_ctrl_parallel_lc_esc 35.320s 9729.424us 1 1 100.00
otp_ctrl_sec_cm 488.010s 37188.481us 1 1 100.00
sec_cm_lci_fsm_local_esc 1 1 100.00
otp_ctrl_parallel_lc_esc 35.320s 9729.424us 1 1 100.00
sec_cm_kdi_fsm_local_esc 1 1 100.00
otp_ctrl_parallel_lc_esc 35.320s 9729.424us 1 1 100.00
sec_cm_part_fsm_local_esc 1 2 50.00
otp_ctrl_parallel_lc_esc 35.320s 9729.424us 1 1 100.00
otp_ctrl_macro_errs 8.390s 705.444us 0 1 0.00
sec_cm_scrmbl_fsm_local_esc 1 1 100.00
otp_ctrl_parallel_lc_esc 35.320s 9729.424us 1 1 100.00
sec_cm_timer_fsm_local_esc 2 2 100.00
otp_ctrl_parallel_lc_esc 35.320s 9729.424us 1 1 100.00
otp_ctrl_sec_cm 488.010s 37188.481us 1 1 100.00
sec_cm_dai_fsm_global_esc 2 2 100.00
otp_ctrl_parallel_lc_esc 35.320s 9729.424us 1 1 100.00
otp_ctrl_sec_cm 488.010s 37188.481us 1 1 100.00
sec_cm_lci_fsm_global_esc 1 1 100.00
otp_ctrl_parallel_lc_esc 35.320s 9729.424us 1 1 100.00
sec_cm_kdi_fsm_global_esc 1 1 100.00
otp_ctrl_parallel_lc_esc 35.320s 9729.424us 1 1 100.00
sec_cm_part_fsm_global_esc 1 2 50.00
otp_ctrl_parallel_lc_esc 35.320s 9729.424us 1 1 100.00
otp_ctrl_macro_errs 8.390s 705.444us 0 1 0.00
sec_cm_scrmbl_fsm_global_esc 1 1 100.00
otp_ctrl_parallel_lc_esc 35.320s 9729.424us 1 1 100.00
sec_cm_timer_fsm_global_esc 2 2 100.00
otp_ctrl_parallel_lc_esc 35.320s 9729.424us 1 1 100.00
otp_ctrl_sec_cm 488.010s 37188.481us 1 1 100.00
sec_cm_part_data_reg_integrity 0 1 0.00
otp_ctrl_init_fail 4.110s 287.001us 0 1 0.00
sec_cm_part_data_reg_bkgn_chk 1 1 100.00
otp_ctrl_check_fail 16.770s 10760.994us 1 1 100.00
sec_cm_part_mem_regren 0 1 0.00
otp_ctrl_dai_lock 2.990s 184.124us 0 1 0.00
sec_cm_part_mem_sw_unreadable 0 1 0.00
otp_ctrl_dai_lock 2.990s 184.124us 0 1 0.00
sec_cm_part_mem_sw_unwritable 0 1 0.00
otp_ctrl_dai_lock 2.990s 184.124us 0 1 0.00
sec_cm_lc_part_mem_sw_noaccess 0 1 0.00
otp_ctrl_dai_lock 2.990s 184.124us 0 1 0.00
sec_cm_access_ctrl_mubi 0 1 0.00
otp_ctrl_dai_lock 2.990s 184.124us 0 1 0.00
sec_cm_token_valid_ctrl_mubi 1 1 100.00
otp_ctrl_smoke 7.070s 393.051us 1 1 100.00
sec_cm_lc_ctrl_intersig_mubi 0 1 0.00
otp_ctrl_dai_lock 2.990s 184.124us 0 1 0.00
sec_cm_test_bus_lc_gated 1 1 100.00
otp_ctrl_smoke 7.070s 393.051us 1 1 100.00
sec_cm_test_tl_lc_gate_fsm_sparse 1 1 100.00
otp_ctrl_sec_cm 488.010s 37188.481us 1 1 100.00
sec_cm_direct_access_config_regwen 1 1 100.00
otp_ctrl_regwen 9.560s 300.112us 1 1 100.00
sec_cm_check_trigger_config_regwen 1 1 100.00
otp_ctrl_smoke 7.070s 393.051us 1 1 100.00
sec_cm_check_config_regwen 1 1 100.00
otp_ctrl_smoke 7.070s 393.051us 1 1 100.00
sec_cm_macro_mem_integrity 0 1 0.00
otp_ctrl_macro_errs 8.390s 705.444us 0 1 0.00
Testpoint Test Max Runtime Sim Time Pass Total %
otp_ctrl_low_freq_read 0 1 0.00
otp_ctrl_low_freq_read 113.210s 26268.920us 0 1 0.00
stress_all_with_rand_reset 0 1 0.00
otp_ctrl_stress_all_with_rand_reset 45.170s 11677.394us 0 1 0.00

Error Messages

   Test seed line log context
UVM_ERROR (otp_ctrl_scoreboard.sv:1323) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*]) reg name: otp_ctrl_core_reg_block.err_code_* 2 test runs
otp_ctrl_dai_lock 97262137088573439766280606310143408963841896621605577022095604245104965156244 518
UVM_INFO @ 184123563 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all 2638121319516339845421924012669356068326053690501656162017081802181076278095 2387
UVM_INFO @ 107132891 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (cip_base_scoreboard.sv:786) [scoreboard] Check failed item.d_data == exp_data (* [*] vs * [*]) d_data mismatch when d_error = * 2 test runs
otp_ctrl_stress_all_with_rand_reset 38199015752962603011048022952148088023791560440630162033616738165899888352553 4349
UVM_INFO @ 11677394483 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_csr_mem_rw_with_rand_reset 101907768137446538442170925826779466106152890189136523438105771997448104380868 103
UVM_INFO @ 65959613 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (otp_ctrl_base_vseq.sv:215) [otp_ctrl_partition_walk_vseq] Check failed rdata* == exp_data* (* [*] vs * [*]) dai addr *ed* rdata* readout mismatch 1 test run
otp_ctrl_partition_walk 2320322328685323377227265059473693800299971788019330300930922811630720102590 113005
UVM_INFO @ 13565165383 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (otp_ctrl_base_vseq.sv:215) [otp_ctrl_low_freq_read_vseq] Check failed rdata* == exp_data* (* [*] vs * [*]) dai addr *ed* rdata* readout mismatch 1 test run
otp_ctrl_low_freq_read 106855025570262550782074589171156818975184276317356064802857723507871516457179 95
UVM_INFO @ 26268920090 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (csr_utils_pkg.sv:461) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_*] Check failed obs == exp (* [*] vs * [*]) Regname: otp_ctrl_core_reg_block.status.dai_idle reset value: * 1 test run
otp_ctrl_init_fail 16873174082365568139492272885279477651540298414021892827542547829138265723715 2609
UVM_INFO @ 287001127 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (otp_ctrl_scoreboard.sv:674) [scoreboard] Check failed cfg.intr_vif.pins[i] === (intr_en[i] & intr_exp[i]) (* [*] vs * [*]) Interrupt_pin: OtpErr 1 test run
otp_ctrl_background_chks 4876377819138092486022817156200044189943042427326170231831099802973461114636 20204
UVM_INFO @ 6574169871 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (otp_ctrl_scoreboard.sv:1323) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*]) reg name: otp_ctrl_core_reg_block.direct_access_rdata_* 1 test run
otp_ctrl_macro_errs 92056271793271628988168053786275314831229202886569854133888873053603522413216 4797
UVM_INFO @ 705443708 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (otp_ctrl_scoreboard.sv:1323) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*]) reg name: otp_ctrl_core_reg_block.intr_state 1 test run
otp_ctrl_test_access 39267799447921091293131994682682659652569933011987287216522291172909056952120 14668
UVM_INFO @ 580923489 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---