Simulation Results: rom_ctrl/32kb

 
01/09/2026 21:34:42 DVSim: v1.52.0 sha: 4e5c99d json Branch: master Tool: xcelium [24.03-s007]
Coverage statistics
  • Total
  • 84.42 %
  • code
  • 79.12 %
  • assert
  • 96.94 %
  • func
  • 77.20 %
  • block
  • 77.91 %
  • line
  • 78.48 %
  • branch
  • 77.67 %
  • toggle
  • 84.14 %
  • FSM
  • 76.19 %
Validation stages
V1
100.00%
V2
88.89%
V2S
83.33%
V3
0.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
rom_ctrl_smoke 3.000s 1110.221us 1 1 100.00
csr_hw_reset 1 1 100.00
rom_ctrl_csr_hw_reset 3.000s 57.968us 1 1 100.00
csr_rw 1 1 100.00
rom_ctrl_csr_rw 2.000s 51.528us 1 1 100.00
csr_bit_bash 1 1 100.00
rom_ctrl_csr_bit_bash 2.000s 119.632us 1 1 100.00
csr_aliasing 1 1 100.00
rom_ctrl_csr_aliasing 2.000s 64.700us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
rom_ctrl_csr_mem_rw_with_rand_reset 3.000s 124.780us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
rom_ctrl_csr_rw 2.000s 51.528us 1 1 100.00
rom_ctrl_csr_aliasing 2.000s 64.700us 1 1 100.00
mem_walk 1 1 100.00
rom_ctrl_mem_walk 2.000s 50.714us 1 1 100.00
mem_partial_access 1 1 100.00
rom_ctrl_mem_partial_access 2.000s 74.485us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
max_throughput_chk 0 1 0.00
rom_ctrl_max_throughput_chk 2.000s 171.988us 0 1 0.00
stress_all 1 1 100.00
rom_ctrl_stress_all 7.000s 96.912us 1 1 100.00
kmac_err_chk 1 1 100.00
rom_ctrl_kmac_err_chk 3.000s 55.589us 1 1 100.00
alert_test 1 1 100.00
rom_ctrl_alert_test 2.000s 51.354us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
rom_ctrl_tl_errors 3.000s 387.672us 1 1 100.00
tl_d_illegal_access 1 1 100.00
rom_ctrl_tl_errors 3.000s 387.672us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
rom_ctrl_csr_hw_reset 3.000s 57.968us 1 1 100.00
rom_ctrl_csr_rw 2.000s 51.528us 1 1 100.00
rom_ctrl_csr_aliasing 2.000s 64.700us 1 1 100.00
rom_ctrl_same_csr_outstanding 2.000s 148.246us 1 1 100.00
tl_d_partial_access 4 4 100.00
rom_ctrl_csr_hw_reset 3.000s 57.968us 1 1 100.00
rom_ctrl_csr_rw 2.000s 51.528us 1 1 100.00
rom_ctrl_csr_aliasing 2.000s 64.700us 1 1 100.00
rom_ctrl_same_csr_outstanding 2.000s 148.246us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
corrupt_sig_fatal_chk 0 1 0.00
rom_ctrl_corrupt_sig_fatal_chk 3600.000s 0.000us 0 1 0.00
passthru_mem_tl_intg_err 1 1 100.00
rom_ctrl_passthru_mem_tl_intg_err 7.000s 807.188us 1 1 100.00
tl_intg_err 2 2 100.00
rom_ctrl_sec_cm 124.000s 986.495us 1 1 100.00
rom_ctrl_tl_intg_err 28.000s 479.040us 1 1 100.00
prim_fsm_check 1 1 100.00
rom_ctrl_sec_cm 124.000s 986.495us 1 1 100.00
prim_count_check 1 1 100.00
rom_ctrl_sec_cm 124.000s 986.495us 1 1 100.00
sec_cm_checker_ctr_consistency 0 1 0.00
rom_ctrl_corrupt_sig_fatal_chk 3600.000s 0.000us 0 1 0.00
sec_cm_checker_ctrl_flow_consistency 0 1 0.00
rom_ctrl_corrupt_sig_fatal_chk 3600.000s 0.000us 0 1 0.00
sec_cm_checker_fsm_local_esc 0 1 0.00
rom_ctrl_corrupt_sig_fatal_chk 3600.000s 0.000us 0 1 0.00
sec_cm_compare_ctrl_flow_consistency 0 1 0.00
rom_ctrl_corrupt_sig_fatal_chk 3600.000s 0.000us 0 1 0.00
sec_cm_compare_ctr_consistency 0 1 0.00
rom_ctrl_corrupt_sig_fatal_chk 3600.000s 0.000us 0 1 0.00
sec_cm_compare_ctr_redun 1 1 100.00
rom_ctrl_sec_cm 124.000s 986.495us 1 1 100.00
sec_cm_fsm_sparse 1 1 100.00
rom_ctrl_sec_cm 124.000s 986.495us 1 1 100.00
sec_cm_mem_scramble 1 1 100.00
rom_ctrl_smoke 3.000s 1110.221us 1 1 100.00
sec_cm_mem_digest 1 1 100.00
rom_ctrl_smoke 3.000s 1110.221us 1 1 100.00
sec_cm_intersig_mubi 1 1 100.00
rom_ctrl_smoke 3.000s 1110.221us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
rom_ctrl_tl_intg_err 28.000s 479.040us 1 1 100.00
sec_cm_bus_local_esc 1 2 50.00
rom_ctrl_corrupt_sig_fatal_chk 3600.000s 0.000us 0 1 0.00
rom_ctrl_kmac_err_chk 3.000s 55.589us 1 1 100.00
sec_cm_mux_mubi 0 1 0.00
rom_ctrl_corrupt_sig_fatal_chk 3600.000s 0.000us 0 1 0.00
sec_cm_mux_consistency 0 1 0.00
rom_ctrl_corrupt_sig_fatal_chk 3600.000s 0.000us 0 1 0.00
sec_cm_ctrl_redun 0 1 0.00
rom_ctrl_corrupt_sig_fatal_chk 3600.000s 0.000us 0 1 0.00
sec_cm_ctrl_mem_integrity 1 1 100.00
rom_ctrl_passthru_mem_tl_intg_err 7.000s 807.188us 1 1 100.00
sec_cm_tlul_fifo_ctr_redun 1 1 100.00
rom_ctrl_sec_cm 124.000s 986.495us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 0 1 0.00
rom_ctrl_stress_all_with_rand_reset 3600.000s 0.000us 0 1 0.00

Error Messages

   Test seed line log context
Job timed out after * minutes 2 test runs
rom_ctrl_corrupt_sig_fatal_chk 104900251306593118508310179351265813599850825594838222713405900210368353880543 None
rom_ctrl_stress_all_with_rand_reset 108207520414215347519232351255168886554410821317346304785843614044532215006535 None
UVM_ERROR (rom_ctrl_throughput_vseq.sv:52) [rom_ctrl_throughput_vseq] Check failed num_cycles == num_mem_reads + * (* [*] vs * [*]) 1 test run
rom_ctrl_max_throughput_chk 89442894610598749053251017365202544063764240970333931302766681081506748348587 88
UVM_INFO @ 171987569 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---