Simulation Results: rstmgr

 
01/09/2026 21:34:42 DVSim: v1.52.0 sha: 4e5c99d json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 97.03 %
  • code
  • 99.38 %
  • assert
  • 98.35 %
  • func
  • 93.37 %
  • line
  • 99.19 %
  • branch
  • 99.72 %
  • cond
  • 99.09 %
  • toggle
  • 99.52 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
rstmgr_smoke 1.730s 74.342us 1 1 100.00
csr_hw_reset 1 1 100.00
rstmgr_csr_hw_reset 1.410s 64.382us 1 1 100.00
csr_rw 1 1 100.00
rstmgr_csr_rw 1.370s 40.866us 1 1 100.00
csr_bit_bash 1 1 100.00
rstmgr_csr_bit_bash 4.850s 81.647us 1 1 100.00
csr_aliasing 1 1 100.00
rstmgr_csr_aliasing 1.330s 37.474us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
rstmgr_csr_mem_rw_with_rand_reset 1.950s 104.854us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
rstmgr_csr_rw 1.370s 40.866us 1 1 100.00
rstmgr_csr_aliasing 1.330s 37.474us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
reset_stretcher 1 1 100.00
rstmgr_por_stretcher 1.420s 63.161us 1 1 100.00
sw_rst 1 1 100.00
rstmgr_sw_rst 1.470s 44.576us 1 1 100.00
sw_rst_reset_race 1 1 100.00
rstmgr_sw_rst_reset_race 1.530s 74.052us 1 1 100.00
reset_info 1 1 100.00
rstmgr_reset 8.550s 680.028us 1 1 100.00
cpu_info 1 1 100.00
rstmgr_reset 8.550s 680.028us 1 1 100.00
alert_info 1 1 100.00
rstmgr_reset 8.550s 680.028us 1 1 100.00
reset_info_capture 1 1 100.00
rstmgr_reset 8.550s 680.028us 1 1 100.00
stress_all 1 1 100.00
rstmgr_stress_all 30.320s 3205.818us 1 1 100.00
alert_test 1 1 100.00
rstmgr_alert_test 1.310s 36.619us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
rstmgr_tl_errors 2.480s 45.481us 1 1 100.00
tl_d_illegal_access 1 1 100.00
rstmgr_tl_errors 2.480s 45.481us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
rstmgr_csr_hw_reset 1.410s 64.382us 1 1 100.00
rstmgr_csr_rw 1.370s 40.866us 1 1 100.00
rstmgr_csr_aliasing 1.330s 37.474us 1 1 100.00
rstmgr_same_csr_outstanding 1.440s 42.682us 1 1 100.00
tl_d_partial_access 4 4 100.00
rstmgr_csr_hw_reset 1.410s 64.382us 1 1 100.00
rstmgr_csr_rw 1.370s 40.866us 1 1 100.00
rstmgr_csr_aliasing 1.330s 37.474us 1 1 100.00
rstmgr_same_csr_outstanding 1.440s 42.682us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
rstmgr_sec_cm 55.810s 7118.377us 1 1 100.00
rstmgr_tl_intg_err 7.640s 815.280us 1 1 100.00
prim_count_check 1 1 100.00
rstmgr_sec_cm 55.810s 7118.377us 1 1 100.00
prim_fsm_check 1 1 100.00
rstmgr_sec_cm 55.810s 7118.377us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
rstmgr_tl_intg_err 7.640s 815.280us 1 1 100.00
sec_cm_scan_intersig_mubi 1 1 100.00
rstmgr_sec_cm_scan_intersig_mubi 1.750s 68.547us 1 1 100.00
sec_cm_leaf_rst_bkgn_chk 1 1 100.00
rstmgr_leaf_rst_cnsty 6.150s 467.272us 1 1 100.00
sec_cm_leaf_rst_shadow 1 1 100.00
rstmgr_leaf_rst_shadow_attack 2.980s 291.915us 1 1 100.00
sec_cm_leaf_fsm_sparse 1 1 100.00
rstmgr_sec_cm 55.810s 7118.377us 1 1 100.00
sec_cm_sw_rst_config_regwen 1 1 100.00
rstmgr_csr_rw 1.370s 40.866us 1 1 100.00
sec_cm_dump_ctrl_config_regwen 1 1 100.00
rstmgr_csr_rw 1.370s 40.866us 1 1 100.00