Simulation Results: rv_timer

 
01/09/2026 21:34:42 DVSim: v1.52.0 sha: 4e5c99d json Branch: master Tool: xcelium [24.03-s007]
Coverage statistics
  • Total
  • 95.76 %
  • code
  • 90.45 %
  • assert
  • 96.84 %
  • func
  • 100.00 %
  • block
  • 99.10 %
  • line
  • 99.02 %
  • branch
  • 99.26 %
  • toggle
  • 73.08 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
V3
33.33%
Testpoint Test Max Runtime Sim Time Pass Total %
random 1 1 100.00
rv_timer_random 2.000s 346.296us 1 1 100.00
csr_hw_reset 1 1 100.00
rv_timer_csr_hw_reset 1.000s 29.195us 1 1 100.00
csr_rw 1 1 100.00
rv_timer_csr_rw 1.000s 12.024us 1 1 100.00
csr_bit_bash 1 1 100.00
rv_timer_csr_bit_bash 3.000s 183.204us 1 1 100.00
csr_aliasing 1 1 100.00
rv_timer_csr_aliasing 1.000s 11.594us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
rv_timer_csr_mem_rw_with_rand_reset 1.000s 18.175us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
rv_timer_csr_rw 1.000s 12.024us 1 1 100.00
rv_timer_csr_aliasing 1.000s 11.594us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
random_reset 1 1 100.00
rv_timer_random_reset 2.000s 61.030us 1 1 100.00
disabled 1 1 100.00
rv_timer_disabled 4.000s 2807.212us 1 1 100.00
cfg_update_on_fly 1 1 100.00
rv_timer_cfg_update_on_fly 75.000s 64442.931us 1 1 100.00
no_interrupt_test 1 1 100.00
rv_timer_cfg_update_on_fly 75.000s 64442.931us 1 1 100.00
stress 1 1 100.00
rv_timer_stress_all 11.000s 5518.077us 1 1 100.00
alert_test 1 1 100.00
rv_timer_alert_test 1.000s 45.901us 1 1 100.00
intr_test 1 1 100.00
rv_timer_intr_test 1.000s 27.925us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
rv_timer_tl_errors 3.000s 144.710us 1 1 100.00
tl_d_illegal_access 1 1 100.00
rv_timer_tl_errors 3.000s 144.710us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
rv_timer_csr_hw_reset 1.000s 29.195us 1 1 100.00
rv_timer_csr_rw 1.000s 12.024us 1 1 100.00
rv_timer_csr_aliasing 1.000s 11.594us 1 1 100.00
rv_timer_same_csr_outstanding 2.000s 24.348us 1 1 100.00
tl_d_partial_access 4 4 100.00
rv_timer_csr_hw_reset 1.000s 29.195us 1 1 100.00
rv_timer_csr_rw 1.000s 12.024us 1 1 100.00
rv_timer_csr_aliasing 1.000s 11.594us 1 1 100.00
rv_timer_same_csr_outstanding 2.000s 24.348us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
rv_timer_sec_cm 2.000s 76.170us 1 1 100.00
rv_timer_tl_intg_err 2.000s 144.406us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
rv_timer_tl_intg_err 2.000s 144.406us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
min_value 0 1 0.00
rv_timer_min 2.000s 641.170us 0 1 0.00
max_value 0 1 0.00
rv_timer_max 1.000s 204.228us 0 1 0.00
stress_all_with_rand_reset 1 1 100.00
rv_timer_stress_all_with_rand_reset 37.000s 4570.891us 1 1 100.00

Error Messages

   Test seed line log context
UVM_FATAL (rv_timer_base_vseq.sv:183) [intr_state_spinwait] timeout rv_timer_reg_block.intr_state* (addr=*) == * 1 test run
rv_timer_min 106489575793929018652122480796930828555512973676107485681118216579304905625347 84
UVM_INFO @ 641169925 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (rv_timer_scoreboard.sv:227) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*]) 1 test run
rv_timer_max 95986983603228131390879536885662962997914035203644646214343133306655642461679 84
UVM_INFO @ 204228479 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---