Simulation Results: spi_device/1r1w

 
01/09/2026 21:34:42 DVSim: v1.52.0 sha: 4e5c99d json Branch: master Tool: xcelium [24.03-s007]
Coverage statistics
  • Total
  • 83.61 %
  • code
  • 89.22 %
  • assert
  • 95.40 %
  • func
  • 66.20 %
  • block
  • 98.29 %
  • line
  • 98.69 %
  • branch
  • 96.89 %
  • toggle
  • 72.75 %
  • FSM
  • 88.54 %
Validation stages
V1
100.00%
V2
92.59%
V2S
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
spi_device_flash_and_tpm 328.000s 24564.665us 1 1 100.00
csr_hw_reset 1 1 100.00
spi_device_csr_hw_reset 3.000s 46.434us 1 1 100.00
csr_rw 1 1 100.00
spi_device_csr_rw 3.000s 168.202us 1 1 100.00
csr_bit_bash 1 1 100.00
spi_device_csr_bit_bash 13.000s 529.780us 1 1 100.00
csr_aliasing 1 1 100.00
spi_device_csr_aliasing 3.000s 101.699us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
spi_device_csr_mem_rw_with_rand_reset 5.000s 170.249us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
spi_device_csr_rw 3.000s 168.202us 1 1 100.00
spi_device_csr_aliasing 3.000s 101.699us 1 1 100.00
mem_walk 1 1 100.00
spi_device_mem_walk 2.000s 10.834us 1 1 100.00
mem_partial_access 1 1 100.00
spi_device_mem_partial_access 3.000s 55.624us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
csb_read 1 1 100.00
spi_device_csb_read 2.000s 63.288us 1 1 100.00
mem_parity 0 1 0.00
spi_device_mem_parity 2.000s 1.890us 0 1 0.00
mem_cfg 0 1 0.00
spi_device_ram_cfg 2.000s 5.839us 0 1 0.00
tpm_read 1 1 100.00
spi_device_tpm_rw 4.000s 352.980us 1 1 100.00
tpm_write 1 1 100.00
spi_device_tpm_rw 4.000s 352.980us 1 1 100.00
tpm_hw_reg 2 2 100.00
spi_device_tpm_read_hw_reg 2.000s 18.832us 1 1 100.00
spi_device_tpm_sts_read 2.000s 21.334us 1 1 100.00
tpm_fully_random_case 1 1 100.00
spi_device_tpm_all 40.000s 13558.687us 1 1 100.00
pass_cmd_filtering 2 2 100.00
spi_device_pass_cmd_filtering 9.000s 1286.858us 1 1 100.00
spi_device_flash_all 125.000s 5568.765us 1 1 100.00
pass_addr_translation 2 2 100.00
spi_device_pass_addr_payload_swap 20.000s 5222.688us 1 1 100.00
spi_device_flash_all 125.000s 5568.765us 1 1 100.00
pass_payload_translation 2 2 100.00
spi_device_pass_addr_payload_swap 20.000s 5222.688us 1 1 100.00
spi_device_flash_all 125.000s 5568.765us 1 1 100.00
cmd_info_slots 1 1 100.00
spi_device_flash_all 125.000s 5568.765us 1 1 100.00
cmd_read_status 2 2 100.00
spi_device_intercept 5.000s 265.314us 1 1 100.00
spi_device_flash_all 125.000s 5568.765us 1 1 100.00
cmd_read_jedec 2 2 100.00
spi_device_intercept 5.000s 265.314us 1 1 100.00
spi_device_flash_all 125.000s 5568.765us 1 1 100.00
cmd_read_sfdp 2 2 100.00
spi_device_intercept 5.000s 265.314us 1 1 100.00
spi_device_flash_all 125.000s 5568.765us 1 1 100.00
cmd_fast_read 2 2 100.00
spi_device_intercept 5.000s 265.314us 1 1 100.00
spi_device_flash_all 125.000s 5568.765us 1 1 100.00
cmd_read_pipeline 2 2 100.00
spi_device_intercept 5.000s 265.314us 1 1 100.00
spi_device_flash_all 125.000s 5568.765us 1 1 100.00
flash_cmd_upload 1 1 100.00
spi_device_upload 4.000s 183.109us 1 1 100.00
mailbox_command 1 1 100.00
spi_device_mailbox 12.000s 285.954us 1 1 100.00
mailbox_cross_outside_command 1 1 100.00
spi_device_mailbox 12.000s 285.954us 1 1 100.00
mailbox_cross_inside_command 1 1 100.00
spi_device_mailbox 12.000s 285.954us 1 1 100.00
cmd_read_buffer 2 2 100.00
spi_device_flash_mode 10.000s 1092.024us 1 1 100.00
spi_device_read_buffer_direct 8.000s 565.326us 1 1 100.00
cmd_dummy_cycle 2 2 100.00
spi_device_mailbox 12.000s 285.954us 1 1 100.00
spi_device_flash_all 125.000s 5568.765us 1 1 100.00
quad_spi 1 1 100.00
spi_device_flash_all 125.000s 5568.765us 1 1 100.00
dual_spi 1 1 100.00
spi_device_flash_all 125.000s 5568.765us 1 1 100.00
4b_3b_feature 1 1 100.00
spi_device_cfg_cmd 2.000s 47.865us 1 1 100.00
write_enable_disable 1 1 100.00
spi_device_cfg_cmd 2.000s 47.865us 1 1 100.00
flash_mode_ignore_cmds 1 1 100.00
spi_device_flash_mode_ignore_cmds 124.000s 8116.095us 1 1 100.00
TPM_with_flash_or_passthrough_mode 1 1 100.00
spi_device_flash_and_tpm 328.000s 24564.665us 1 1 100.00
tpm_and_flash_trans_with_min_inactive_time 1 1 100.00
spi_device_flash_and_tpm_min_idle 12.000s 2530.314us 1 1 100.00
stress_all 1 1 100.00
spi_device_stress_all 234.000s 42507.197us 1 1 100.00
alert_test 1 1 100.00
spi_device_alert_test 1.000s 20.691us 1 1 100.00
intr_test 1 1 100.00
spi_device_intr_test 2.000s 100.965us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
spi_device_tl_errors 4.000s 351.992us 1 1 100.00
tl_d_illegal_access 1 1 100.00
spi_device_tl_errors 4.000s 351.992us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
spi_device_csr_hw_reset 3.000s 46.434us 1 1 100.00
spi_device_csr_rw 3.000s 168.202us 1 1 100.00
spi_device_csr_aliasing 3.000s 101.699us 1 1 100.00
spi_device_same_csr_outstanding 3.000s 83.821us 1 1 100.00
tl_d_partial_access 4 4 100.00
spi_device_csr_hw_reset 3.000s 46.434us 1 1 100.00
spi_device_csr_rw 3.000s 168.202us 1 1 100.00
spi_device_csr_aliasing 3.000s 101.699us 1 1 100.00
spi_device_same_csr_outstanding 3.000s 83.821us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
spi_device_sec_cm 2.000s 237.969us 1 1 100.00
spi_device_tl_intg_err 22.000s 7234.307us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
spi_device_tl_intg_err 22.000s 7234.307us 1 1 100.00

Error Messages

   Test seed line log context
UVM_ERROR (uvm_hdl_inca.c:743) [UVM/DPI/NOBJ1] name tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.mem[*] cannot be resolved to a hdl object (vlog,vhdl,vlog-slice) 1 test run
spi_device_mem_parity 99060416102538306418139600463432167057777503238070621419005247885595086985117 87
UVM_ERROR @ 1350420 ps: (spi_device_mem_parity_vseq.sv:44) [uvm_test_top.env.virtual_sequencer.spi_device_mem_parity_vseq] Check failed (uvm_hdl_read(egress_path, mem_data))
ERROR: VHPI NOTFOUND
Name tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.mem[944] not found within the scope .
UVM_ERROR @ 1350420 ps: (uvm_hdl_inca.c:743) [UVM/DPI/NOBJ2] name tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.mem[944] cannot be resolved to a hdl object (vlog,vhdl,vlog-slice)
UVM_ERROR (spi_device_ram_cfg_vseq.sv:28) [spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (* [*] vs * [*]) 1 test run
spi_device_ram_cfg 114332524018586472971930229735971386842922050057953243421977856787207007611321 85
UVM_ERROR @ 3288882 ps: (spi_device_ram_cfg_vseq.sv:28) [uvm_test_top.env.virtual_sequencer.spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (0x3d5 [1111010101] vs 0x0 [0])
UVM_ERROR @ 3341882 ps: (spi_device_ram_cfg_vseq.sv:28) [uvm_test_top.env.virtual_sequencer.spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (0x95 [10010101] vs 0x0 [0])
UVM_ERROR @ 3420882 ps: (spi_device_ram_cfg_vseq.sv:28) [uvm_test_top.env.virtual_sequencer.spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (0x13d [100111101] vs 0x0 [0])
UVM_ERROR @ 3471882 ps: (spi_device_ram_cfg_vseq.sv:28) [uvm_test_top.env.virtual_sequencer.spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (0xec [11101100] vs 0x0 [0])