Simulation Results: spi_host

 
01/09/2026 21:34:42 DVSim: v1.52.0 sha: 4e5c99d json Branch: master Tool: xcelium [24.03-s007]
Coverage statistics
  • Total
  • 92.41 %
  • code
  • 91.14 %
  • assert
  • 96.60 %
  • func
  • 89.50 %
  • block
  • 96.78 %
  • line
  • 98.54 %
  • branch
  • 92.95 %
  • toggle
  • 73.07 %
  • FSM
  • 100.00 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
spi_host_smoke 16.000s 1492.741us 1 1 100.00
csr_hw_reset 1 1 100.00
spi_host_csr_hw_reset 2.000s 30.976us 1 1 100.00
csr_rw 1 1 100.00
spi_host_csr_rw 2.000s 29.275us 1 1 100.00
csr_bit_bash 1 1 100.00
spi_host_csr_bit_bash 2.000s 84.040us 1 1 100.00
csr_aliasing 1 1 100.00
spi_host_csr_aliasing 1.000s 17.496us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
spi_host_csr_mem_rw_with_rand_reset 2.000s 101.818us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
spi_host_csr_rw 2.000s 29.275us 1 1 100.00
spi_host_csr_aliasing 1.000s 17.496us 1 1 100.00
mem_walk 1 1 100.00
spi_host_mem_walk 1.000s 22.526us 1 1 100.00
mem_partial_access 1 1 100.00
spi_host_mem_partial_access 2.000s 41.526us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
performance 1 1 100.00
spi_host_performance 2.000s 27.975us 1 1 100.00
error_event_intr 3 3 100.00
spi_host_overflow_underflow 4.000s 118.909us 1 1 100.00
spi_host_error_cmd 2.000s 104.995us 1 1 100.00
spi_host_event 4.000s 1008.098us 1 1 100.00
clock_rate 1 1 100.00
spi_host_speed 2.000s 31.699us 1 1 100.00
speed 1 1 100.00
spi_host_speed 2.000s 31.699us 1 1 100.00
chip_select_timing 1 1 100.00
spi_host_speed 2.000s 31.699us 1 1 100.00
upper_range_clkdiv 1 1 100.00
spi_host_upper_range_clkdiv 236.000s 19219.392us 1 1 100.00
sw_reset 1 1 100.00
spi_host_sw_reset 7.000s 719.410us 1 1 100.00
passthrough_mode 1 1 100.00
spi_host_passthrough_mode 1.000s 41.155us 1 1 100.00
cpol_cpha 1 1 100.00
spi_host_speed 2.000s 31.699us 1 1 100.00
full_cycle 1 1 100.00
spi_host_speed 2.000s 31.699us 1 1 100.00
duplex 1 1 100.00
spi_host_smoke 16.000s 1492.741us 1 1 100.00
tx_rx_only 1 1 100.00
spi_host_smoke 16.000s 1492.741us 1 1 100.00
stress_all 1 1 100.00
spi_host_stress_all 45.000s 2311.688us 1 1 100.00
spien 1 1 100.00
spi_host_spien 5.000s 2165.130us 1 1 100.00
stall 1 1 100.00
spi_host_status_stall 69.000s 5771.556us 1 1 100.00
Idlecsbactive 1 1 100.00
spi_host_idlecsbactive 2.000s 136.820us 1 1 100.00
data_fifo_status 1 1 100.00
spi_host_overflow_underflow 4.000s 118.909us 1 1 100.00
alert_test 1 1 100.00
spi_host_alert_test 1.000s 48.541us 1 1 100.00
intr_test 1 1 100.00
spi_host_intr_test 1.000s 46.702us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
spi_host_tl_errors 1.000s 126.377us 1 1 100.00
tl_d_illegal_access 1 1 100.00
spi_host_tl_errors 1.000s 126.377us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
spi_host_csr_hw_reset 2.000s 30.976us 1 1 100.00
spi_host_csr_rw 2.000s 29.275us 1 1 100.00
spi_host_csr_aliasing 1.000s 17.496us 1 1 100.00
spi_host_same_csr_outstanding 2.000s 64.056us 1 1 100.00
tl_d_partial_access 4 4 100.00
spi_host_csr_hw_reset 2.000s 30.976us 1 1 100.00
spi_host_csr_rw 2.000s 29.275us 1 1 100.00
spi_host_csr_aliasing 1.000s 17.496us 1 1 100.00
spi_host_same_csr_outstanding 2.000s 64.056us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
spi_host_tl_intg_err 2.000s 405.532us 1 1 100.00
spi_host_sec_cm 2.000s 877.320us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
spi_host_tl_intg_err 2.000s 405.532us 1 1 100.00