Simulation Results: sram_ctrl/main

 
01/09/2026 21:34:42 DVSim: v1.52.0 sha: 4e5c99d json Branch: master Tool: xcelium [24.03-s007]
Coverage statistics
  • Total
  • 94.99 %
  • code
  • 94.73 %
  • assert
  • 97.83 %
  • func
  • 92.40 %
  • block
  • 94.07 %
  • line
  • 95.05 %
  • branch
  • 92.05 %
  • toggle
  • 91.84 %
  • FSM
  • 100.00 %
Validation stages
V1
100.00%
V2
100.00%
V2S
80.00%
V3
0.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
sram_ctrl_smoke 4.000s 866.064us 1 1 100.00
csr_hw_reset 1 1 100.00
sram_ctrl_csr_hw_reset 1.000s 16.809us 1 1 100.00
csr_rw 1 1 100.00
sram_ctrl_csr_rw 1.000s 29.511us 1 1 100.00
csr_bit_bash 1 1 100.00
sram_ctrl_csr_bit_bash 2.000s 115.483us 1 1 100.00
csr_aliasing 1 1 100.00
sram_ctrl_csr_aliasing 1.000s 12.288us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
sram_ctrl_csr_mem_rw_with_rand_reset 4.000s 2325.910us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
sram_ctrl_csr_rw 1.000s 29.511us 1 1 100.00
sram_ctrl_csr_aliasing 1.000s 12.288us 1 1 100.00
mem_walk 1 1 100.00
sram_ctrl_mem_walk 332.000s 130873.374us 1 1 100.00
mem_partial_access 1 1 100.00
sram_ctrl_mem_partial_access 117.000s 4694.947us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
multiple_keys 1 1 100.00
sram_ctrl_multiple_keys 26.000s 7742.411us 1 1 100.00
stress_pipeline 1 1 100.00
sram_ctrl_stress_pipeline 207.000s 15677.789us 1 1 100.00
bijection 1 1 100.00
sram_ctrl_bijection 163.000s 4317.065us 1 1 100.00
access_during_key_req 1 1 100.00
sram_ctrl_access_during_key_req 10.000s 1384.427us 1 1 100.00
lc_escalation 1 1 100.00
sram_ctrl_lc_escalation 33.000s 8348.158us 1 1 100.00
executable 1 1 100.00
sram_ctrl_executable 19.000s 12880.321us 1 1 100.00
partial_access 2 2 100.00
sram_ctrl_partial_access 4.000s 357.471us 1 1 100.00
sram_ctrl_partial_access_b2b 364.000s 271930.650us 1 1 100.00
max_throughput 3 3 100.00
sram_ctrl_max_throughput 7.000s 1333.146us 1 1 100.00
sram_ctrl_throughput_w_partial_write 4.000s 702.004us 1 1 100.00
sram_ctrl_throughput_w_readback 4.000s 711.277us 1 1 100.00
regwen 1 1 100.00
sram_ctrl_regwen 7.000s 551.618us 1 1 100.00
ram_cfg 1 1 100.00
sram_ctrl_ram_cfg 5.000s 2580.460us 1 1 100.00
non_pow2_mem_size 3 3 100.00
sram_ctrl_smoke 4.000s 866.064us 1 1 100.00
sram_ctrl_partial_access 4.000s 357.471us 1 1 100.00
sram_ctrl_access_during_key_req 10.000s 1384.427us 1 1 100.00
stress_all 1 1 100.00
sram_ctrl_stress_all 367.000s 104309.803us 1 1 100.00
alert_test 1 1 100.00
sram_ctrl_alert_test 2.000s 22.605us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
sram_ctrl_tl_errors 5.000s 150.520us 1 1 100.00
tl_d_illegal_access 1 1 100.00
sram_ctrl_tl_errors 5.000s 150.520us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
sram_ctrl_csr_hw_reset 1.000s 16.809us 1 1 100.00
sram_ctrl_csr_rw 1.000s 29.511us 1 1 100.00
sram_ctrl_csr_aliasing 1.000s 12.288us 1 1 100.00
sram_ctrl_same_csr_outstanding 2.000s 17.966us 1 1 100.00
tl_d_partial_access 4 4 100.00
sram_ctrl_csr_hw_reset 1.000s 16.809us 1 1 100.00
sram_ctrl_csr_rw 1.000s 29.511us 1 1 100.00
sram_ctrl_csr_aliasing 1.000s 12.288us 1 1 100.00
sram_ctrl_same_csr_outstanding 2.000s 17.966us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
passthru_mem_tl_intg_err 1 1 100.00
sram_ctrl_passthru_mem_tl_intg_err 44.000s 100495.024us 1 1 100.00
tl_intg_err 2 2 100.00
sram_ctrl_sec_cm 5.000s 2801.220us 1 1 100.00
sram_ctrl_tl_intg_err 2.000s 131.630us 1 1 100.00
prim_count_check 1 1 100.00
sram_ctrl_sec_cm 5.000s 2801.220us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
sram_ctrl_tl_intg_err 2.000s 131.630us 1 1 100.00
sec_cm_ctrl_config_regwen 1 1 100.00
sram_ctrl_regwen 7.000s 551.618us 1 1 100.00
sec_cm_readback_config_regwen 1 1 100.00
sram_ctrl_regwen 7.000s 551.618us 1 1 100.00
sec_cm_exec_config_regwen 1 1 100.00
sram_ctrl_csr_rw 1.000s 29.511us 1 1 100.00
sec_cm_exec_config_mubi 1 1 100.00
sram_ctrl_executable 19.000s 12880.321us 1 1 100.00
sec_cm_exec_intersig_mubi 1 1 100.00
sram_ctrl_executable 19.000s 12880.321us 1 1 100.00
sec_cm_lc_hw_debug_en_intersig_mubi 1 1 100.00
sram_ctrl_executable 19.000s 12880.321us 1 1 100.00
sec_cm_lc_escalate_en_intersig_mubi 1 1 100.00
sram_ctrl_lc_escalation 33.000s 8348.158us 1 1 100.00
sec_cm_prim_ram_ctrl_mubi 0 1 0.00
sram_ctrl_mubi_enc_err 3600.000s 0.000us 0 1 0.00
sec_cm_mem_integrity 1 1 100.00
sram_ctrl_passthru_mem_tl_intg_err 44.000s 100495.024us 1 1 100.00
sec_cm_mem_readback 0 1 0.00
sram_ctrl_readback_err 3600.000s 0.000us 0 1 0.00
sec_cm_mem_scramble 1 1 100.00
sram_ctrl_smoke 4.000s 866.064us 1 1 100.00
sec_cm_addr_scramble 1 1 100.00
sram_ctrl_smoke 4.000s 866.064us 1 1 100.00
sec_cm_instr_bus_lc_gated 1 1 100.00
sram_ctrl_executable 19.000s 12880.321us 1 1 100.00
sec_cm_ram_tl_lc_gate_fsm_sparse 1 1 100.00
sram_ctrl_sec_cm 5.000s 2801.220us 1 1 100.00
sec_cm_key_global_esc 1 1 100.00
sram_ctrl_lc_escalation 33.000s 8348.158us 1 1 100.00
sec_cm_key_local_esc 1 1 100.00
sram_ctrl_sec_cm 5.000s 2801.220us 1 1 100.00
sec_cm_init_ctr_redun 1 1 100.00
sram_ctrl_sec_cm 5.000s 2801.220us 1 1 100.00
sec_cm_scramble_key_sideload 1 1 100.00
sram_ctrl_smoke 4.000s 866.064us 1 1 100.00
sec_cm_tlul_fifo_ctr_redun 1 1 100.00
sram_ctrl_sec_cm 5.000s 2801.220us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 0 1 0.00
sram_ctrl_stress_all_with_rand_reset 7.000s 184.721us 0 1 0.00

Error Messages

   Test seed line log context
Job timed out after * minutes 2 test runs
sram_ctrl_readback_err 80533054397219602650371481552835398517492649275504001017025747705135653534010 None
sram_ctrl_mubi_enc_err 71681268566714445176197396194231022968602633574473136546684452129103227509086 None
UVM_ERROR (tl_host_driver.sv:148) [driver] Check failed seq_item_port.has_do_available() == * (* [*] vs * [*]) 1 test run
sram_ctrl_stress_all_with_rand_reset 41427019285110950563675671184335366085809606998603097580121820165810437021774 110
UVM_INFO @ 184720986 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---