Simulation Results: uart

 
01/09/2026 21:34:42 DVSim: v1.52.0 sha: 4e5c99d json Branch: master Tool: xcelium [24.03-s007]
Coverage statistics
  • Total
  • 93.70 %
  • code
  • 92.73 %
  • assert
  • 97.69 %
  • func
  • 90.69 %
  • block
  • 99.08 %
  • line
  • 99.52 %
  • branch
  • 98.34 %
  • toggle
  • 73.08 %
  • FSM
  • 100.00 %
Validation stages
V1
100.00%
V2
95.45%
V2S
100.00%
V3
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
uart_smoke 4.000s 489.542us 1 1 100.00
csr_hw_reset 1 1 100.00
uart_csr_hw_reset 1.000s 34.116us 1 1 100.00
csr_rw 1 1 100.00
uart_csr_rw 1.000s 47.602us 1 1 100.00
csr_bit_bash 1 1 100.00
uart_csr_bit_bash 3.000s 282.285us 1 1 100.00
csr_aliasing 1 1 100.00
uart_csr_aliasing 1.000s 21.388us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
uart_csr_mem_rw_with_rand_reset 2.000s 97.080us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
uart_csr_rw 1.000s 47.602us 1 1 100.00
uart_csr_aliasing 1.000s 21.388us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
base_random_seq 1 1 100.00
uart_tx_rx 18.000s 9892.920us 1 1 100.00
parity 2 2 100.00
uart_smoke 4.000s 489.542us 1 1 100.00
uart_tx_rx 18.000s 9892.920us 1 1 100.00
parity_error 2 2 100.00
uart_intr 11.000s 13579.334us 1 1 100.00
uart_rx_parity_err 28.000s 52312.577us 1 1 100.00
watermark 2 2 100.00
uart_tx_rx 18.000s 9892.920us 1 1 100.00
uart_intr 11.000s 13579.334us 1 1 100.00
fifo_full 1 1 100.00
uart_fifo_full 18.000s 80142.021us 1 1 100.00
fifo_overflow 1 1 100.00
uart_fifo_overflow 49.000s 19970.286us 1 1 100.00
fifo_reset 1 1 100.00
uart_fifo_reset 36.000s 101555.888us 1 1 100.00
rx_frame_err 1 1 100.00
uart_intr 11.000s 13579.334us 1 1 100.00
rx_break_err 1 1 100.00
uart_intr 11.000s 13579.334us 1 1 100.00
rx_timeout 1 1 100.00
uart_intr 11.000s 13579.334us 1 1 100.00
perf 1 1 100.00
uart_perf 82.000s 12085.186us 1 1 100.00
sys_loopback 1 1 100.00
uart_loopback 9.000s 5615.745us 1 1 100.00
line_loopback 1 1 100.00
uart_loopback 9.000s 5615.745us 1 1 100.00
rx_noise_filter 0 1 0.00
uart_noise_filter 28.000s 111585.920us 0 1 0.00
rx_start_bit_filter 1 1 100.00
uart_rx_start_bit_filter 4.000s 3342.069us 1 1 100.00
tx_overide 1 1 100.00
uart_tx_ovrd 2.000s 218.090us 1 1 100.00
rx_oversample 1 1 100.00
uart_rx_oversample 41.000s 6205.343us 1 1 100.00
long_b2b_transfer 1 1 100.00
uart_long_xfer_wo_dly 172.000s 90965.987us 1 1 100.00
stress_all 1 1 100.00
uart_stress_all 536.000s 302893.534us 1 1 100.00
alert_test 1 1 100.00
uart_alert_test 2.000s 22.625us 1 1 100.00
intr_test 1 1 100.00
uart_intr_test 2.000s 14.876us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
uart_tl_errors 2.000s 67.663us 1 1 100.00
tl_d_illegal_access 1 1 100.00
uart_tl_errors 2.000s 67.663us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
uart_csr_hw_reset 1.000s 34.116us 1 1 100.00
uart_csr_rw 1.000s 47.602us 1 1 100.00
uart_csr_aliasing 1.000s 21.388us 1 1 100.00
uart_same_csr_outstanding 1.000s 36.949us 1 1 100.00
tl_d_partial_access 4 4 100.00
uart_csr_hw_reset 1.000s 34.116us 1 1 100.00
uart_csr_rw 1.000s 47.602us 1 1 100.00
uart_csr_aliasing 1.000s 21.388us 1 1 100.00
uart_same_csr_outstanding 1.000s 36.949us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
uart_sec_cm 1.000s 65.713us 1 1 100.00
uart_tl_intg_err 1.000s 79.650us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
uart_tl_intg_err 1.000s 79.650us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 1 1 100.00
uart_stress_all_with_rand_reset 33.000s 2316.670us 1 1 100.00

Error Messages

   Test seed line log context
UVM_ERROR (uart_scoreboard.sv:376) [scoreboard] Check failed get_field_val(ral.status.rxempty, item.d_data) == rx_empty_exp (* [*] vs * [*]) check rx_empty fail: uart_rx_clk_pulses = *, rx_q.size = * 1 test run
uart_noise_filter 51274779765904672931104840573008929919207010534736372105517459390064384430848 94
UVM_ERROR @ 108251857518 ps: (uart_scoreboard.sv:392) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0
UVM_ERROR @ 108251857518 ps: (csr_utils_pkg.sv:463) [csr_utils_pkg::csr_rd_check.isolation_fork.unmblk1] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: uart_reg_block.status.rxidle reset value: 0x1
UVM_ERROR @ 108361545018 ps: (uart_scoreboard.sv:499) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] rxlvl mismatch exp: 1 (+/-1), act: 3, clk_pulses: 0
UVM_ERROR @ 108362170018 ps: (uart_scoreboard.sv:529) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (97 [0x61] vs 247 [0xf7]) reg name: uart_reg_block.rdata