Simulation Results: ac_range_check

 
02/09/2026 21:28:39 DVSim: v1.52.0 sha: e5cd915 json Branch: master Tool: xcelium [24.03-s007]
Coverage statistics
  • Total
  • 82.86 %
  • code
  • 93.03 %
  • assert
  • 97.75 %
  • func
  • 57.79 %
  • block
  • 99.10 %
  • line
  • 99.93 %
  • branch
  • 98.24 %
  • toggle
  • 80.91 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
V3
100.00%
unmapped
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
ac_range_check_smoke 1 1 100.00
ac_range_check_smoke 43.000s 1480.382us 1 1 100.00
ac_range_check_smoke_racl 1 1 100.00
ac_range_check_smoke_racl 58.000s 4282.227us 1 1 100.00
csr_hw_reset 1 1 100.00
ac_range_check_csr_hw_reset 10.000s 22.264us 1 1 100.00
csr_rw 1 1 100.00
ac_range_check_csr_rw 9.000s 20.085us 1 1 100.00
csr_bit_bash 1 1 100.00
ac_range_check_csr_bit_bash 37.000s 709.936us 1 1 100.00
csr_aliasing 1 1 100.00
ac_range_check_csr_aliasing 14.000s 509.063us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
ac_range_check_csr_mem_rw_with_rand_reset 9.000s 82.246us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
ac_range_check_csr_rw 9.000s 20.085us 1 1 100.00
ac_range_check_csr_aliasing 14.000s 509.063us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
ac_range_check_lock_range 1 1 100.00
ac_range_check_lock_range 10.000s 67.850us 1 1 100.00
ac_range_bypass_enable 1 1 100.00
ac_range_check_bypass 31.000s 1263.362us 1 1 100.00
stress_all 1 1 100.00
ac_range_check_stress_all 116.000s 1805.587us 1 1 100.00
alert_test 1 1 100.00
ac_range_check_alert_test 9.000s 24.392us 1 1 100.00
intr_test 1 1 100.00
ac_range_check_intr_test 9.000s 24.550us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
ac_range_check_tl_errors 3.000s 26.673us 1 1 100.00
tl_d_illegal_access 1 1 100.00
ac_range_check_tl_errors 3.000s 26.673us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
ac_range_check_csr_hw_reset 10.000s 22.264us 1 1 100.00
ac_range_check_csr_rw 9.000s 20.085us 1 1 100.00
ac_range_check_csr_aliasing 14.000s 509.063us 1 1 100.00
ac_range_check_same_csr_outstanding 12.000s 2952.919us 1 1 100.00
tl_d_partial_access 4 4 100.00
ac_range_check_csr_hw_reset 10.000s 22.264us 1 1 100.00
ac_range_check_csr_rw 9.000s 20.085us 1 1 100.00
ac_range_check_csr_aliasing 14.000s 509.063us 1 1 100.00
ac_range_check_same_csr_outstanding 12.000s 2952.919us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
shadow_reg_update_error 1 1 100.00
ac_range_check_shadow_reg_errors 25.000s 3875.551us 1 1 100.00
shadow_reg_read_clear_staged_value 1 1 100.00
ac_range_check_shadow_reg_errors 25.000s 3875.551us 1 1 100.00
shadow_reg_storage_error 1 1 100.00
ac_range_check_shadow_reg_errors 25.000s 3875.551us 1 1 100.00
shadowed_reset_glitch 1 1 100.00
ac_range_check_shadow_reg_errors 25.000s 3875.551us 1 1 100.00
shadow_reg_update_error_with_csr_rw 1 1 100.00
ac_range_check_shadow_reg_errors_with_csr_rw 83.000s 1416.659us 1 1 100.00
tl_intg_err 2 2 100.00
ac_range_check_sec_cm 7.000s 52.374us 1 1 100.00
ac_range_check_tl_intg_err 11.000s 411.979us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 1 1 100.00
ac_range_check_stress_all_with_rand_reset 354.000s 1894.846us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
Unmapped 1 1 100.00
ac_range_check_smoke_high_threshold 43.000s 2682.937us 1 1 100.00