Simulation Results

Simulation Results: aes/gcm_masked

02/09/2026 21:28:39 DVSim: v1.52.0 sha: e5cd915 json Branch: master Tool: xcelium [24.03-s007]

Coverage statistics

Total
85.34 %

code
96.13 %

assert
98.43 %

func
61.47 %

block
96.40 %

line
97.52 %

branch
91.55 %

toggle
98.05 %

FSM
97.42 %

Validation stages

V1		100.00%
V2		84.21%
V2S		77.78%
V3		0.00%

7/7 passed

100.00 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
wake_up				1	1	100.00
	aes_wake_up	3.000s	67.503us	1	1	100.00
smoke				1	1	100.00
	aes_smoke	5.000s	177.882us	1	1	100.00
csr_hw_reset				1	1	100.00
	aes_csr_hw_reset	2.000s	68.427us	1	1	100.00
csr_rw				1	1	100.00
	aes_csr_rw	2.000s	115.965us	1	1	100.00
csr_bit_bash				1	1	100.00
	aes_csr_bit_bash	11.000s	2486.442us	1	1	100.00
csr_aliasing				1	1	100.00
	aes_csr_aliasing	2.000s	59.893us	1	1	100.00
csr_mem_rw_with_rand_reset				1	1	100.00
	aes_csr_mem_rw_with_rand_reset	3.000s	70.610us	1	1	100.00
regwen_csr_and_corresponding_lockable_csr				2	2	100.00
	aes_csr_rw	2.000s	115.965us	1	1	100.00
	aes_csr_aliasing	2.000s	59.893us	1	1	100.00

16/19 passed

84.21 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
algorithm				2	3	66.67
	aes_smoke	5.000s	177.882us	1	1	100.00
	aes_config_error	4.000s	123.531us	0	1	0.00
	aes_stress	7.000s	100.666us	1	1	100.00
key_length				2	3	66.67
	aes_smoke	5.000s	177.882us	1	1	100.00
	aes_config_error	4.000s	123.531us	0	1	0.00
	aes_stress	7.000s	100.666us	1	1	100.00
back2back				2	2	100.00
	aes_stress	7.000s	100.666us	1	1	100.00
	aes_b2b	18.000s	2584.066us	1	1	100.00
backpressure				1	1	100.00
	aes_stress	7.000s	100.666us	1	1	100.00
multi_message				2	4	50.00
	aes_smoke	5.000s	177.882us	1	1	100.00
	aes_config_error	4.000s	123.531us	0	1	0.00
	aes_stress	7.000s	100.666us	1	1	100.00
	aes_alert_reset	3464.000s	200000.000us	0	1	0.00
failure_test				1	3	33.33
	aes_man_cfg_err	3.000s	65.550us	1	1	100.00
	aes_config_error	4.000s	123.531us	0	1	0.00
	aes_alert_reset	3464.000s	200000.000us	0	1	0.00
trigger_clear_test				1	1	100.00
	aes_clear	3.000s	96.315us	1	1	100.00
nist_test_vectors				1	1	100.00
	aes_nist_vectors	10.000s	340.654us	1	1	100.00
nist_test_vectors_gcm				1	1	100.00
	aes_nist_vectors_gcm	11.000s	540.280us	1	1	100.00
reset_recovery				0	1	0.00
	aes_alert_reset	3464.000s	200000.000us	0	1	0.00
stress				1	1	100.00
	aes_stress	7.000s	100.666us	1	1	100.00
sideload				2	2	100.00
	aes_stress	7.000s	100.666us	1	1	100.00
	aes_sideload	6.000s	858.513us	1	1	100.00
deinitialization				1	1	100.00
	aes_deinit	5.000s	282.952us	1	1	100.00
stress_all				0	1	0.00
	aes_stress_all	7.000s	429.983us	0	1	0.00
gcm_save_and_restore				1	1	100.00
	aes_gcm_save_restore	3.000s	239.112us	1	1	100.00
alert_test				1	1	100.00
	aes_alert_test	2.000s	64.899us	1	1	100.00
tl_d_oob_addr_access				1	1	100.00
	aes_tl_errors	2.000s	65.986us	1	1	100.00
tl_d_illegal_access				1	1	100.00
	aes_tl_errors	2.000s	65.986us	1	1	100.00
tl_d_outstanding_access				4	4	100.00
	aes_csr_hw_reset	2.000s	68.427us	1	1	100.00
	aes_csr_rw	2.000s	115.965us	1	1	100.00
	aes_csr_aliasing	2.000s	59.893us	1	1	100.00
	aes_same_csr_outstanding	3.000s	236.117us	1	1	100.00
tl_d_partial_access				4	4	100.00
	aes_csr_hw_reset	2.000s	68.427us	1	1	100.00
	aes_csr_rw	2.000s	115.965us	1	1	100.00
	aes_csr_aliasing	2.000s	59.893us	1	1	100.00
	aes_same_csr_outstanding	3.000s	236.117us	1	1	100.00

V2S

14/18 passed

77.78 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
reseeding				0	1	0.00
	aes_reseed	4.000s	68.105us	0	1	0.00
fault_inject				2	3	66.67
	aes_fi	6.000s	351.873us	0	1	0.00
	aes_control_fi	3.000s	147.984us	1	1	100.00
	aes_cipher_fi	3.000s	115.618us	1	1	100.00
shadow_reg_update_error				1	1	100.00
	aes_shadow_reg_errors	3.000s	195.342us	1	1	100.00
shadow_reg_read_clear_staged_value				1	1	100.00
	aes_shadow_reg_errors	3.000s	195.342us	1	1	100.00
shadow_reg_storage_error				1	1	100.00
	aes_shadow_reg_errors	3.000s	195.342us	1	1	100.00
shadowed_reset_glitch				1	1	100.00
	aes_shadow_reg_errors	3.000s	195.342us	1	1	100.00
shadow_reg_update_error_with_csr_rw				1	1	100.00
	aes_shadow_reg_errors_with_csr_rw	4.000s	186.236us	1	1	100.00
tl_intg_err				2	2	100.00
	aes_sec_cm	8.000s	640.899us	1	1	100.00
	aes_tl_intg_err	3.000s	281.194us	1	1	100.00
sec_cm_bus_integrity				1	1	100.00
	aes_tl_intg_err	3.000s	281.194us	1	1	100.00
sec_cm_lc_escalate_en_intersig_mubi				0	1	0.00
	aes_alert_reset	3464.000s	200000.000us	0	1	0.00
sec_cm_main_config_shadow				1	1	100.00
	aes_shadow_reg_errors	3.000s	195.342us	1	1	100.00
sec_cm_gcm_config_shadow				1	1	100.00
	aes_shadow_reg_errors	3.000s	195.342us	1	1	100.00
sec_cm_main_config_sparse				3	4	75.00
	aes_smoke	5.000s	177.882us	1	1	100.00
	aes_stress	7.000s	100.666us	1	1	100.00
	aes_alert_reset	3464.000s	200000.000us	0	1	0.00
	aes_core_fi	6.000s	360.585us	1	1	100.00
sec_cm_gcm_config_sparse				3	4	75.00
	aes_gcm_save_restore	3.000s	239.112us	1	1	100.00
	aes_config_error	4.000s	123.531us	0	1	0.00
	aes_stress	7.000s	100.666us	1	1	100.00
	aes_core_fi	6.000s	360.585us	1	1	100.00
sec_cm_aux_config_shadow				1	1	100.00
	aes_shadow_reg_errors	3.000s	195.342us	1	1	100.00
sec_cm_aux_config_regwen				2	2	100.00
	aes_readability	3.000s	93.630us	1	1	100.00
	aes_stress	7.000s	100.666us	1	1	100.00
sec_cm_key_sideload				2	2	100.00
	aes_stress	7.000s	100.666us	1	1	100.00
	aes_sideload	6.000s	858.513us	1	1	100.00
sec_cm_key_sw_unreadable				1	1	100.00
	aes_readability	3.000s	93.630us	1	1	100.00
sec_cm_data_reg_sw_unreadable				1	1	100.00
	aes_readability	3.000s	93.630us	1	1	100.00
sec_cm_key_sec_wipe				1	1	100.00
	aes_readability	3.000s	93.630us	1	1	100.00
sec_cm_iv_config_sec_wipe				1	1	100.00
	aes_readability	3.000s	93.630us	1	1	100.00
sec_cm_data_reg_sec_wipe				1	1	100.00
	aes_readability	3.000s	93.630us	1	1	100.00
sec_cm_data_reg_key_sca				1	1	100.00
	aes_stress	7.000s	100.666us	1	1	100.00
sec_cm_key_masking				1	1	100.00
	aes_stress	7.000s	100.666us	1	1	100.00
sec_cm_main_fsm_sparse				0	1	0.00
	aes_fi	6.000s	351.873us	0	1	0.00
sec_cm_main_fsm_redun				3	4	75.00
	aes_fi	6.000s	351.873us	0	1	0.00
	aes_control_fi	3.000s	147.984us	1	1	100.00
	aes_cipher_fi	3.000s	115.618us	1	1	100.00
	aes_ctr_fi	3.000s	88.455us	1	1	100.00
sec_cm_cipher_fsm_sparse				0	1	0.00
	aes_fi	6.000s	351.873us	0	1	0.00
sec_cm_cipher_fsm_redun				2	3	66.67
	aes_fi	6.000s	351.873us	0	1	0.00
	aes_control_fi	3.000s	147.984us	1	1	100.00
	aes_cipher_fi	3.000s	115.618us	1	1	100.00
sec_cm_cipher_ctr_redun				1	1	100.00
	aes_cipher_fi	3.000s	115.618us	1	1	100.00
sec_cm_ctr_fsm_sparse				0	1	0.00
	aes_fi	6.000s	351.873us	0	1	0.00
sec_cm_ctr_fsm_redun				2	3	66.67
	aes_fi	6.000s	351.873us	0	1	0.00
	aes_control_fi	3.000s	147.984us	1	1	100.00
	aes_ctr_fi	3.000s	88.455us	1	1	100.00
sec_cm_ghash_fsm_sparse				0	1	0.00
	aes_fi	6.000s	351.873us	0	1	0.00
sec_cm_ctrl_sparse				3	4	75.00
	aes_fi	6.000s	351.873us	0	1	0.00
	aes_control_fi	3.000s	147.984us	1	1	100.00
	aes_cipher_fi	3.000s	115.618us	1	1	100.00
	aes_ctr_fi	3.000s	88.455us	1	1	100.00
sec_cm_main_fsm_global_esc				0	1	0.00
	aes_alert_reset	3464.000s	200000.000us	0	1	0.00
sec_cm_main_fsm_local_esc				3	4	75.00
	aes_fi	6.000s	351.873us	0	1	0.00
	aes_control_fi	3.000s	147.984us	1	1	100.00
	aes_cipher_fi	3.000s	115.618us	1	1	100.00
	aes_ctr_fi	3.000s	88.455us	1	1	100.00
sec_cm_cipher_fsm_local_esc				3	4	75.00
	aes_fi	6.000s	351.873us	0	1	0.00
	aes_control_fi	3.000s	147.984us	1	1	100.00
	aes_cipher_fi	3.000s	115.618us	1	1	100.00
	aes_ctr_fi	3.000s	88.455us	1	1	100.00
sec_cm_ctr_fsm_local_esc				2	3	66.67
	aes_fi	6.000s	351.873us	0	1	0.00
	aes_control_fi	3.000s	147.984us	1	1	100.00
	aes_ctr_fi	3.000s	88.455us	1	1	100.00
sec_cm_ghash_fsm_local_esc				1	2	50.00
	aes_ghash_fi	2.000s	113.015us	1	1	100.00
	aes_fi	6.000s	351.873us	0	1	0.00
sec_cm_data_reg_local_esc				2	3	66.67
	aes_fi	6.000s	351.873us	0	1	0.00
	aes_control_fi	3.000s	147.984us	1	1	100.00
	aes_cipher_fi	3.000s	115.618us	1	1	100.00

0/1 passed

0.00 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
stress_all_with_rand_reset				0	1	0.00
	aes_stress_all_with_rand_reset	74.000s	5296.687us	0	1	0.00

Error Messages

	Test	seed	line	log context
UVM_ERROR (uvm_sequencer_base.svh:757) sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'sequencer' for sequence 'parent_sequence' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues				2 test runs
	aes_reseed	30502226327708078942161712547874696504805016733200847299368330254312899583540	9779	UVM_INFO @ 68104919 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	aes_stress_all	91722513173788359633947936713792867555000023361872168080944340023749010264555	20320	UVM_INFO @ 429982893 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
xmsim: E,MEMALC: Memory not allocated for actual argument 'input_msg', passed to DPI task/function 'c_dpi_aes_crypt_message' call at line '' in file '/nightly/current_run/scratch/master/aes_gcm_masked-sim-xcelium/default/fusesoc-work/src/lowrisc_dv_aes_env_/aes_scoreboard.sv' at time PS + *.				1 test run
	aes_config_error	50101870244490497998635878763940780088232698419150074637182106263660573151942	6418	xmsim: E,MEMALC: Memory not allocated for actual argument 'input_msg', passed to DPI task/function 'c_dpi_aes_crypt_message' call at line '745' in file '/nightly/current_run/scratch/master/aes_gcm_masked-sim-xcelium/default/fusesoc-work/src/lowrisc_dv_aes_env_0.1/aes_scoreboard.sv' at time 52306649 PS + 10. xmsim: E,MEMALC: Memory not allocated for actual argument 'input_msg', passed to DPI task/function 'c_dpi_aes_crypt_message' call at line '745' in file '/nightly/current_run/scratch/master/aes_gcm_masked-sim-xcelium/default/fusesoc-work/src/lowrisc_dv_aes_env_0.1/aes_scoreboard.sv' at time 52306649 PS + 10. ERROR: Decryption finalizing failed xmsim: *E,MEMALC: Memory not allocated for actual argument 'predicted_msg', passed to DPI task/function 'c_dpi_aes_crypt_message' call at line '745' in file '/nightly/current_run/scratch/master/aes_gcm_masked-sim-xcelium/default/fusesoc-work/src/lowrisc_dv_aes_env_0.1/aes_scoreboard.sv' at time 52306649 PS + 10.
UVM_FATAL (uvm_phase.svh:1521) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue				1 test run
	aes_alert_reset	6926973675669960659959089644224527611482654678047152412529138813213627857416	1971970	UVM_INFO @ 200000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_FATAL (aes_scoreboard.sv:923) scoreboard [scoreboard]				1 test run
	aes_fi	100765409899590983882012055743993731194611962490529898016353757529437815225549	10386	----\| NO FAILURES BUT NUMBER OF EXPECTED MESSAGES DOES NOT MATCH ACTUAL ----\| Expected: 5 ----\| Seen: 4 ----\| Expected corrupted: 0
UVM_FATAL (aes_base_vseq.sv:334) virtual_sequencer [aes_stress_vseq] Expected GCM phase GCM_AAD, got GCM_TEXT				1 test run
	aes_stress_all_with_rand_reset	87686341049719653074816543570126378968667027618959977936723274911696422749701	1685	UVM_INFO @ 5296687386 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---